Andy Ross e6dfae0fea soc/intel_adsp: Fix linker warning ... The linker will emit a warning condition when a section with a declared alignment doesn't naturally start on that alignment (which begets the question of why the declared alignment syntax exists at all...). Do the alignment for .bss between the sections instead as a simple workaround. Note that this alignment isn't architecturally required, as current Zephyr targets don't use the page-aligned pseudo-MMU on this hardware; the only requirement is alignment to the 64 byte cache stride. It should work to pack .bss tightly. But when I try that, I get an error from the rimage tool, which is apparently unprepared for non-4k-aligned sections? Signed-off-by: Andy Ross <andrew.j.ross@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>		2020-10-21 06:38:53 -04:00
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arc	soc: arc: Increase cpu frequency for nsim_hs_smp	2020-09-16 14:35:31 -05:00
arm	nrf53: soc.c: Replace bespoke nrf53_has_erratum19() with MDK variant	2020-10-20 12:28:54 +02:00
nios2	soc: nios2: Cleanup linker scripts to use new DTS macros	2020-04-30 20:59:13 -05:00
posix	zephyr: replace zephyr integer types with C99 types	2020-06-08 08:23:57 -05:00
riscv	soc: riscv: litex-vexriscv: change CSR accessors	2020-10-02 11:36:16 +02:00
x86	x86: add common memory.ld	2020-09-30 14:14:07 -07:00
xtensa	soc/intel_adsp: Fix linker warning	2020-10-21 06:38:53 -04:00
Kconfig	timing: introduce timing functions as a generic feature	2020-09-05 13:28:38 -05:00