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https://github.com/zephyrproject-rtos/zephyr
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98fd9d0975
This extends litex_vexriscv.dts file by adding clock controller nodes. Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
87 lines
919 B
Plaintext
87 lines
919 B
Plaintext
/*
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* Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <riscv32-litex-vexriscv.dtsi>
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/ {
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model = "LiteX VexRiscV";
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compatible = "litex,vexriscv";
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &ram0;
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};
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ram0: memory@40000000 {
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device_type = "memory";
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reg = <0x40000000 0x10000000>;
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};
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};
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&uart0 {
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status = "okay";
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current-speed = <115200>;
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};
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&timer0 {
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status = "okay";
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};
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ð0 {
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status = "okay";
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};
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&dna0 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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};
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&prbs0 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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label = "I2C_0";
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};
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&pwm0 {
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status = "okay";
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};
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&gpio_out {
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status = "okay";
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};
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&gpio_in {
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status = "okay";
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};
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&i2s_rx {
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status = "okay";
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};
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&i2s_tx {
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status = "okay";
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};
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&clk0 {
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status = "okay";
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};
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&clk1 {
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status = "okay";
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};
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&clock0 {
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status = "okay";
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};
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