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f7fffae8aa
Change all the Intel and Wind River code license from BSD-3 to Apache 2. Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Allan Stephens <allan.stephens@windriver.com> Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
88 lines
2.4 KiB
Plaintext
88 lines
2.4 KiB
Plaintext
# Kconfig - interrupt controller configuration options
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#
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# Copyright (c) 2015 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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menu "Interrupt Controllers"
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config LOAPIC
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bool "LOAPIC"
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default n
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select IOAPIC
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depends on X86_32
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help
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This option selects local APIC as the interrupt controller.
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config LOAPIC_DEBUG
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bool "LOAPIC Debug"
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default n
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depends on LOAPIC
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help
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This option enable debugging for the LOAPIC driver.
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config LOAPIC_BASE_ADDRESS
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hex "Local APIC Base Address"
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default 0xFEE00000
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depends on LOAPIC
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help
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This option specifies the base address of the Local APIC device.
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config IOAPIC
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bool "IO-APIC"
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default y
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depends on LOAPIC
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help
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This option signifies that the target has an IO-APIC device. This
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capability allows IO-APIC-dependent code to be included.
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config IOAPIC_DEBUG
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bool "IO-APIC Debugging"
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default n
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depends on IOAPIC
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help
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Enable debugging for IO-APIC driver.
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config IOAPIC_BASE_ADDRESS
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hex "IO-APIC Base Address"
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default 0xFEC00000
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depends on IOAPIC
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help
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This option specifies the base address of the IO-APIC device.
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config IOAPIC_NUM_RTES
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int "Number of Redirection Table Entries available"
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default 24
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depends on IOAPIC
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help
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This option indicates the maximum number of Redirection Table Entries
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(RTEs) (one per IRQ available to the IO-APIC) made available to the
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kernel, regardless of the number provided by the hardware itself. For
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most efficient usage of memory, it should match the number of IRQ lines
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needed by devices connected to the IO-APIC.
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config ARCV2_INTERRUPT_UNIT
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bool "ARCv2 Interrupt Unit"
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default y
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depends on ARC
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help
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The ARCv2 interrupt unit has 16 allocated exceptions associated with
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vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255.
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The interrupt unit is optional in the ARCv2-based processors. When
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building a processor, you can configure the processor to include an
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interrupt unit. The ARCv2 interrupt unit is highly programmable.
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endmenu
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