mirror of
https://github.com/zephyrproject-rtos/zephyr
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1f4b5ddd0f
With the upcoming riscv64 support, it is best to use "riscv" as the subdirectory name and common symbols as riscv32 and riscv64 support code is almost identical. Then later decide whether 32-bit or 64-bit compilation is wanted. Redirects for the web documentation are also included. Then zephyrbot complained about this: " New files added that are not covered in CODEOWNERS: dts/riscv/microsemi-miv.dtsi dts/riscv/riscv32-fe310.dtsi Please add one or more entries in the CODEOWNERS file to cover those files " So I assigned them to those who created them. Feel free to readjust as necessary. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
98 lines
2.9 KiB
Plaintext
98 lines
2.9 KiB
Plaintext
#
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# Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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menu "RISCV Options"
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depends on RISCV
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config ARCH
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string
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default "riscv64" if 64BIT
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default "riscv32"
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menu "RISCV Processor Options"
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config INCLUDE_RESET_VECTOR
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bool "Include Reset vector"
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help
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Include the reset vector stub, which initializes the stack and
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prepares for running C code.
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config RISCV_SOC_CONTEXT_SAVE
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bool "Enable SOC-based context saving in IRQ handlers"
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select RISCV_SOC_OFFSETS
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help
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Enable low-level SOC-specific context management, for SOCs
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with extra state that must be saved when entering an
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interrupt/exception, and restored on exit. If unsure, leave
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this at the default value.
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Enabling this option requires that the SoC provide a
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soc_context.h header which defines the following macros:
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- SOC_ESF_MEMBERS: structure component declarations to
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allocate space for. The last such declaration should not
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end in a semicolon, for portability. The generic RISC-V
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architecture code will allocate space for these members in
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a "struct soc_esf" type (typedefed to soc_esf_t), which will
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be available if arch.h is included.
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- SOC_ESF_INIT: structure contents initializer for struct soc_esf
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state. The last initialized member should not end in a comma.
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The generic architecture IRQ wrapper will also call
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\_\_soc_save_context and \_\_soc_restore_context routines at
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ISR entry and exit, respectively. These should typically
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be implemented in assembly. If they were C functions, they
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would have these signatures:
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``void __soc_save_context(soc_esf_t *state);``
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``void __soc_restore_context(soc_esf_t *state);``
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The calls obey standard calling conventions; i.e., the state
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pointer address is in a0, and ra contains the return address.
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config RISCV_SOC_OFFSETS
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bool "Enable SOC-based offsets"
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help
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Enabling this option requires that the SoC provide a soc_offsets.h
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header which defines the following macros:
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- GEN_SOC_OFFSET_SYMS(): a macro which expands to
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GEN_OFFSET_SYM(soc_esf_t, soc_specific_member) calls
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to ensure offset macros for SOC_ESF_MEMBERS are defined
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in offsets.h. The last one should not end in a semicolon.
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See gen_offset.h for more details.
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config RISCV_SOC_INTERRUPT_INIT
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bool "Enable SOC-based interrupt initialization"
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help
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Enable SOC-based interrupt initialization
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(call soc_interrupt_init, within _IntLibInit when enabled)
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config RISCV_GENERIC_TOOLCHAIN
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bool "Compile using generic riscv32 toolchain"
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default y
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help
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Compile using generic riscv32 toolchain.
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Allow SOCs that have custom extended riscv ISA to still
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compile with generic riscv32 toolchain.
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config RISCV_HAS_CPU_IDLE
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bool "Does SOC has CPU IDLE instruction"
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help
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Does SOC has CPU IDLE instruction
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config GEN_ISR_TABLES
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default y
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config GEN_IRQ_VECTOR_TABLE
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default n
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endmenu
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endmenu
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