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https://github.com/zephyrproject-rtos/zephyr
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With the upcoming riscv64 support, it is best to use "riscv" as the subdirectory name and common symbols as riscv32 and riscv64 support code is almost identical. Then later decide whether 32-bit or 64-bit compilation is wanted. Redirects for the web documentation are also included. Then zephyrbot complained about this: " New files added that are not covered in CODEOWNERS: dts/riscv/microsemi-miv.dtsi dts/riscv/riscv32-fe310.dtsi Please add one or more entries in the CODEOWNERS file to cover those files " So I assigned them to those who created them. Feel free to readjust as necessary. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
65 lines
1.3 KiB
ArmAsm
65 lines
1.3 KiB
ArmAsm
/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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* Contributors: 2018 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel_structs.h>
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/* exports */
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GTEXT(__initialize)
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GTEXT(__reset)
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/* imports */
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GTEXT(_PrepC)
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#if CONFIG_INCLUDE_RESET_VECTOR
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SECTION_FUNC(reset, __reset)
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/*
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* jump to __initialize
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* use call opcode in case __initialize is far away.
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* This will be dependent on linker.ld configuration.
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*/
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call __initialize
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#endif /* CONFIG_INCLUDE_RESET_VECTOR */
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/* use ABI name of registers for the sake of simplicity */
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/*
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* Remainder of asm-land initialization code before we can jump into
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* the C domain
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*/
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SECTION_FUNC(TEXT, __initialize)
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#ifdef CONFIG_INIT_STACKS
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/* Pre-populate all bytes in _interrupt_stack with 0xAA */
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la t0, _interrupt_stack
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li t1, CONFIG_ISR_STACK_SIZE
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add t1, t1, t0
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/* Populate _interrupt_stack with 0xaaaaaaaa */
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li t2, 0xaaaaaaaa
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aa_loop:
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sw t2, 0x00(t0)
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addi t0, t0, 4
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blt t0, t1, aa_loop
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#endif
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/*
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* Initially, setup stack pointer to
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* _interrupt_stack + CONFIG_ISR_STACK_SIZE
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*/
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la sp, _interrupt_stack
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li t0, CONFIG_ISR_STACK_SIZE
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add sp, sp, t0
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#ifdef CONFIG_WDOG_INIT
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call _WdogInit
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#endif
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/*
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* Jump into C domain. _PrepC zeroes BSS, copies rw data into RAM,
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* and then enters kernel z_cstart
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*/
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call _PrepC
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