mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-08 04:32:41 +00:00
db09c2905b
Enable arc to access the i2c controller on I/O fabric. There are two i2c controllers on quark se SoC. One is attached to the I/O fabric and the other one is in the sensor system. X86 cpu is only able to access the i2c controller on the I/O fabric and the access is supported by existing code. HW allows arc to access both controllers. But, the existing code only gives arc access to the controller in the sensor sub-system. Let's grant arc the access to the controller on I/O fabric as well by the following changes. 1. Add i2c_qmsi.c into arc compilation. 2. Use the already defined macros to choose interrupt numbers and do interrupt unmasking automatically based on the compilation targets. 3. Add new symbols in Kconfig including driver names for both controllers Jira: ZEP-1189 Change-Id: I317da6038c50e0c8bd16f446182c1f8bdf6d3ba2 Signed-off-by: Baohong Liu <baohong.liu@intel.com>
323 lines
8.1 KiB
C
323 lines
8.1 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <errno.h>
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#include <device.h>
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#include <i2c.h>
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#include <ioapic.h>
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#include <power.h>
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#include "qm_i2c.h"
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#include "qm_isr.h"
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#include "clk.h"
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#include "soc.h"
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/* Convenient macros to get the controller instance and the driver data. */
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#define GET_CONTROLLER_INSTANCE(dev) \
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(((const struct i2c_qmsi_config_info *) \
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dev->config->config_info)->instance)
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#define GET_DRIVER_DATA(dev) \
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((struct i2c_qmsi_driver_data *)dev->driver_data)
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struct i2c_qmsi_config_info {
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qm_i2c_t instance; /* Controller instance. */
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union dev_config default_cfg;
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clk_periph_t clock_gate;
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};
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static int i2c_qmsi_init(struct device *dev);
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struct i2c_qmsi_driver_data {
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struct k_sem device_sync_sem;
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int transfer_status;
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struct k_sem sem;
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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uint32_t device_power_state;
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#ifdef CONFIG_SYS_POWER_DEEP_SLEEP
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qm_i2c_context_t i2c_ctx;
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#endif
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#endif
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};
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static void i2c_qmsi_set_power_state(struct device *dev, uint32_t power_state)
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{
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struct i2c_qmsi_driver_data *drv_data = dev->driver_data;
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drv_data->device_power_state = power_state;
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}
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static uint32_t i2c_qmsi_get_power_state(struct device *dev)
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{
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struct i2c_qmsi_driver_data *drv_data = dev->driver_data;
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return drv_data->device_power_state;
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}
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#ifdef CONFIG_SYS_POWER_DEEP_SLEEP
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static int i2c_suspend_device(struct device *dev)
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{
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if (device_busy_check(dev)) {
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return -EBUSY;
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}
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struct i2c_qmsi_driver_data *drv_data = GET_DRIVER_DATA(dev);
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qm_i2c_save_context(GET_CONTROLLER_INSTANCE(dev), &drv_data->i2c_ctx);
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i2c_qmsi_set_power_state(dev, DEVICE_PM_SUSPEND_STATE);
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return 0;
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}
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static int i2c_resume_device_from_suspend(struct device *dev)
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{
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struct i2c_qmsi_driver_data *drv_data = GET_DRIVER_DATA(dev);
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qm_i2c_restore_context(GET_CONTROLLER_INSTANCE(dev),
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&drv_data->i2c_ctx);
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i2c_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
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return 0;
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}
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#endif
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/*
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* Implements the driver control management functionality
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* the *context may include IN data or/and OUT data
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*/
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static int i2c_device_ctrl(struct device *dev, uint32_t ctrl_command,
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void *context)
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{
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if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
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#ifdef CONFIG_SYS_POWER_DEEP_SLEEP
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if (*((uint32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
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return i2c_suspend_device(dev);
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} else if (*((uint32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
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return i2c_resume_device_from_suspend(dev);
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}
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#endif
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} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
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*((uint32_t *)context) = i2c_qmsi_get_power_state(dev);
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return 0;
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}
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return 0;
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}
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#else
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#define i2c_qmsi_set_power_state(...)
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#endif /* CONFIG_DEVICE_POWER_MANAGEMENT */
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#ifdef CONFIG_I2C_0
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static struct i2c_qmsi_driver_data driver_data_0;
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static const struct i2c_qmsi_config_info config_info_0 = {
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.instance = QM_I2C_0,
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.default_cfg.raw = CONFIG_I2C_0_DEFAULT_CFG,
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.clock_gate = CLK_PERIPH_I2C_M0_REGISTER | CLK_PERIPH_CLK,
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};
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DEVICE_DEFINE(i2c_0, CONFIG_I2C_0_NAME, &i2c_qmsi_init,
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i2c_device_ctrl, &driver_data_0, &config_info_0, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL);
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#endif /* CONFIG_I2C_0 */
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#ifdef CONFIG_I2C_1
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static struct i2c_qmsi_driver_data driver_data_1;
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static const struct i2c_qmsi_config_info config_info_1 = {
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.instance = QM_I2C_1,
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.default_cfg.raw = CONFIG_I2C_1_DEFAULT_CFG,
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.clock_gate = CLK_PERIPH_I2C_M1_REGISTER | CLK_PERIPH_CLK,
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};
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DEVICE_DEFINE(i2c_1, CONFIG_I2C_1_NAME, &i2c_qmsi_init,
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i2c_device_ctrl, &driver_data_1, &config_info_1, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL);
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#endif /* CONFIG_I2C_1 */
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static int i2c_qmsi_configure(struct device *dev, uint32_t config)
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{
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qm_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
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struct i2c_qmsi_driver_data *driver_data = GET_DRIVER_DATA(dev);
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qm_i2c_reg_t *const controller = QM_I2C[instance];
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union dev_config cfg;
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int rc;
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qm_i2c_config_t qm_cfg;
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cfg.raw = config;
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/* This driver only supports master mode. */
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if (!cfg.bits.is_master_device)
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return -EINVAL;
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qm_cfg.mode = QM_I2C_MASTER;
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qm_cfg.address_mode = (cfg.bits.use_10_bit_addr) ? QM_I2C_10_BIT :
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QM_I2C_7_BIT;
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switch (cfg.bits.speed) {
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case I2C_SPEED_STANDARD:
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qm_cfg.speed = QM_I2C_SPEED_STD;
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break;
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case I2C_SPEED_FAST:
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qm_cfg.speed = QM_I2C_SPEED_FAST;
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break;
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case I2C_SPEED_FAST_PLUS:
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qm_cfg.speed = QM_I2C_SPEED_FAST_PLUS;
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break;
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default:
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return -EINVAL;
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}
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k_sem_take(&driver_data->sem, K_FOREVER);
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rc = qm_i2c_set_config(instance, &qm_cfg);
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k_sem_give(&driver_data->sem);
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controller->ic_sda_hold = (CONFIG_I2C_SDA_RX_HOLD << 16) +
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CONFIG_I2C_SDA_TX_HOLD;
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controller->ic_sda_setup = CONFIG_I2C_SDA_SETUP;
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return rc;
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}
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static void transfer_complete(void *data, int rc, qm_i2c_status_t status,
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uint32_t len)
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{
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struct device *dev = (struct device *) data;
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struct i2c_qmsi_driver_data *driver_data;
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driver_data = GET_DRIVER_DATA(dev);
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driver_data->transfer_status = rc;
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k_sem_give(&driver_data->device_sync_sem);
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}
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static int i2c_qmsi_transfer(struct device *dev, struct i2c_msg *msgs,
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uint8_t num_msgs, uint16_t addr)
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{
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struct i2c_qmsi_driver_data *driver_data = GET_DRIVER_DATA(dev);
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qm_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
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int rc;
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if (msgs == NULL || num_msgs == 0) {
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return -ENOTSUP;
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}
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device_busy_set(dev);
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for (int i = 0; i < num_msgs; i++) {
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uint8_t op = msgs[i].flags & I2C_MSG_RW_MASK;
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bool stop = (msgs[i].flags & I2C_MSG_STOP) == I2C_MSG_STOP;
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qm_i2c_transfer_t xfer = { 0 };
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if (op == I2C_MSG_WRITE) {
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xfer.tx = msgs[i].buf;
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xfer.tx_len = msgs[i].len;
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} else {
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xfer.rx = msgs[i].buf;
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xfer.rx_len = msgs[i].len;
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}
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xfer.callback = transfer_complete;
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xfer.callback_data = dev;
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xfer.stop = stop;
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k_sem_take(&driver_data->sem, K_FOREVER);
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rc = qm_i2c_master_irq_transfer(instance, &xfer, addr);
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k_sem_give(&driver_data->sem);
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if (rc != 0) {
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device_busy_clear(dev);
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return -EIO;
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}
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/* Block current thread until the I2C transfer completes. */
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k_sem_take(&driver_data->device_sync_sem, K_FOREVER);
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if (driver_data->transfer_status != 0) {
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device_busy_clear(dev);
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return -EIO;
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}
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}
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device_busy_clear(dev);
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return 0;
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}
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static const struct i2c_driver_api api = {
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.configure = i2c_qmsi_configure,
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.transfer = i2c_qmsi_transfer,
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};
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static int i2c_qmsi_init(struct device *dev)
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{
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struct i2c_qmsi_driver_data *driver_data = GET_DRIVER_DATA(dev);
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const struct i2c_qmsi_config_info *config = dev->config->config_info;
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qm_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
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int err;
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k_sem_init(&driver_data->device_sync_sem, 0, UINT_MAX);
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k_sem_init(&driver_data->sem, 0, UINT_MAX);
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k_sem_give(&driver_data->sem);
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switch (instance) {
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case QM_I2C_0:
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/* Register interrupt handler, unmask IRQ and route it
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* to Lakemont core.
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*/
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_I2C_0_INT),
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CONFIG_I2C_0_IRQ_PRI, qm_i2c_0_irq_isr, NULL,
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(IOAPIC_LEVEL | IOAPIC_HIGH));
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_I2C_0_INT));
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QM_IR_UNMASK_INTERRUPTS(
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QM_INTERRUPT_ROUTER->i2c_master_0_int_mask);
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break;
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#ifdef CONFIG_I2C_1
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case QM_I2C_1:
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_I2C_1_INT),
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CONFIG_I2C_1_IRQ_PRI, qm_i2c_1_irq_isr, NULL,
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(IOAPIC_LEVEL | IOAPIC_HIGH));
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_I2C_1_INT));
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QM_IR_UNMASK_INTERRUPTS(
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QM_INTERRUPT_ROUTER->i2c_master_1_int_mask);
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break;
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#endif /* CONFIG_I2C_1 */
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default:
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return -EIO;
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}
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clk_periph_enable(config->clock_gate);
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err = i2c_qmsi_configure(dev, config->default_cfg.raw);
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if (err < 0) {
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return err;
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}
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dev->driver_api = &api;
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i2c_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
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return 0;
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}
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