Bradley Bolen eb9515ab9c arch: arm: cortex_r: Add memory barriers for register accesses ... Cortex R has a write buffer that can cause reordering problems when accessing memory mapped registers. Use memory barries to make sure that these accesses are performed in the desired order. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>		2019-08-09 22:50:50 +02:00
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cortex_m
cortex_r	arch: arm: cortex_r: Add memory barriers for register accesses	2019-08-09 22:50:50 +02:00
arch.h	arch: arm: cortex_r: Add memory barriers for register accesses	2019-08-09 22:50:50 +02:00
asm_inline_gcc.h	arch: arm: Add Cortex-R support	2019-08-09 22:50:50 +02:00
asm_inline.h
error.h	arch: arm: Add Cortex-R support	2019-08-09 22:50:50 +02:00
exc.h
irq.h	arch: arm: Add Cortex-R support	2019-08-09 22:50:50 +02:00
misc.h
nmi.h
syscall.h	arch: arm: Add Cortex-R support	2019-08-09 22:50:50 +02:00