Karsten Koenig 2e61137cc9 arch: riscv: thread: Init soc context on stack ... The optional SOC_CONTEXT carries processor state registers that need to be initialized properly to avoid uninitialized memory read as processor state. In particular on the RV32M1 the extra soc context stores a state for special loop instructions, and loading non zero values will have the core assume it is in a loop. Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>		2020-07-13 15:00:19 -05:00
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litex-vexriscv	zephyr: replace zephyr integer types with C99 types	2020-06-08 08:23:57 -05:00
openisa_rv32m1	arch: riscv: thread: Init soc context on stack	2020-07-13 15:00:19 -05:00
riscv-privilege	zephyr: replace zephyr integer types with C99 types	2020-06-08 08:23:57 -05:00
CMakeLists.txt