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zephyr/dts/bindings/riscv
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Shawn Nematbakhsh 3cf0081e60 dts: bindings: riscv: Add and use bindings for sifive CPUs. 
No relevant bindings exist for previous CPU compatible properties, so
add new ones.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2022-04-05 12:00:03 +02:00
..
openisa,rv32m1-pcc.yaml
riscv,cpus.yaml
riscv,sifive-e24.yaml
riscv,sifive-e31.yaml dts: bindings: riscv: Add and use bindings for sifive CPUs. 2022-04-05 12:00:03 +02:00
riscv,sifive-e51.yaml dts: bindings: riscv: Add and use bindings for sifive CPUs. 2022-04-05 12:00:03 +02:00
riscv,sifive-s7.yaml dts: bindings: riscv: Add and use bindings for sifive CPUs. 2022-04-05 12:00:03 +02:00
riscv,sifive.yaml