Eugene Cohen 816229128d arch/arm64: update gicv3 sre enablement ... Fix writing of ICC_SRE_EL3 to or-in bits to align with original intent to read-modify-write this register. Also disable FIQ and IRQ bypass so interrupt delivery occurs through GIC. Platforms may choose to override this behavior in z_arm64_el3_plat_init implementations. Remove ICC_SRE_EL3 config from viper and qemu since this is now handled in the arm64 arch core. Signed-off-by: Eugene Cohen <quic_egmc@quicinc.com>		2022-05-10 09:13:20 +02:00
..
arm	linker: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
bcm_vk	arch/arm64: update gicv3 sre enablement	2022-05-10 09:13:20 +02:00
intel_socfpga	linker: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
nxp_imx	linker: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
nxp_layerscape	linker: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
qemu_cortex_a53	arch/arm64: update gicv3 sre enablement	2022-05-10 09:13:20 +02:00
xenvm	linker: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
CMakeLists.txt
Kconfig