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https://github.com/zephyrproject-rtos/zephyr
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5d0db517b9
Add a new sifive,plic-1.0.0 binding that inherits from the riscv,plic0 binding. The new binding adds a required riscv,ndev property, which gives the number of external interrupts supported. Use the new binding for microsemi-miv.dtsi (with a value of 31 for riscv,ndev, from http://www.actel.com/ipdocs/MiV_RV32IMAF_L1_AHB_HB.pdf) and riscv32-fe310.dtsi (which already assigns riscv,ndev). Also remove a spurious riscv,ndev assignment from riscv32-litex-vexriscv.dtsi. Also make edtlib and the old scripts/dts/ scripts replace '.' in compatible strings with '_' when generating identifiers. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> |
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| .. | ||
| arm,v6m-nvic.yaml | ||
| arm,v7m-nvic.yaml | ||
| arm,v8m-nvic.yaml | ||
| atmel,sam0-eic.yaml | ||
| intel,cavs-intc.yaml | ||
| intel,ioapic.yaml | ||
| openisa,rv32m1-event-unit.yaml | ||
| openisa,rv32m1-intmux.yaml | ||
| riscv,cpu-intc.yaml | ||
| riscv,plic0.yaml | ||
| shared-irq.yaml | ||
| sifive,plic-1.0.0.yaml | ||
| snps,arcv2-intc.yaml | ||
| snps,designware-intc.yaml | ||
| vexriscv,intc0.yaml | ||
| xtensa,intc.yaml | ||