Andrew Boie f0ddbd7eee x86: abstract toplevel page table pointer ... This patch is a preparatory step in enabling the MMU in long mode; no steps are taken to implement long mode support. We introduce struct x86_page_tables, which represents the top-level data structure for page tables: - For 32-bit, this will contain a four-entry page directory pointer table (PDPT) - For 64-bit, this will (eventually) contain a page map level 4 table (PML4) In either case, this pointer value is what gets programmed into CR3 to activate a set of page tables. There are extra bits in CR3 to set for long mode, we'll get around to that later. This abstraction will allow us to use the same APIs that work with page tables in either mode, rather than hard-coding that the top level data structure is a PDPT. z_x86_mmu_validate() has been re-written to make it easier to add another level of paging for long mode, to support 2MB PDPT entries, and correctly validate regions which span PDPTE entries. Some MMU-related APIs moved out of 32-bit x86's arch.h into mmustructs.h. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>		2019-10-04 15:53:49 -07:00
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arc
arm	arm: arch code naming cleanup	2019-10-04 10:46:23 +02:00
common
nios2
posix
riscv
x86	x86: abstract toplevel page table pointer	2019-10-04 15:53:49 -07:00
x86_64
xtensa
cpu.h
syscall.h