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39bb93d402
The combination of CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL and CONFIG_CLOCK_STM32_PLL_SRC_HSI on SOCs with PREDIV1 support made use of the LL define LL_RCC_PLLSOURCE_HSI_DIV_2, which is not defined for SOCs with PREDIV1 support. This exchanges LL_RCC_PLLSOURCE_HSI_DIV_2 with LL_RCC_PLLSOURCE_HSI which is the appropiate source according to stm32f0xx_ll_rcc.h line 473 and stm32f3xx_ll_rcc.h line 795. Tested by compiling hello world for nucleo_f091rc board with HSI as PLLSOURCE. Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
82 lines
1.9 KiB
C
82 lines
1.9 KiB
C
/*
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*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <soc_registers.h>
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#include <clock_control.h>
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#include <misc/util.h>
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#include <clock_control/stm32_clock_control.h>
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#include "stm32_ll_clock.h"
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#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
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/**
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* @brief fill in pll configuration structure
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*/
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void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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{
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/*
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* PLL MUL
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* 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000
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* 3 -> LL_RCC_PLL_MUL_3 -> 0x00040000
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* 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
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* ...
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* 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000
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*/
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pllinit->PLLMul = ((CONFIG_CLOCK_STM32_PLL_MULTIPLIER - 2)
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<< RCC_CFGR_PLLMUL_Pos);
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#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
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/* PREDIV support is a specific RCC configuration present on */
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/* following SoCs: STM32F302XE, STM32F303xE and STM32F398xx */
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/* cf Reference manual for more details */
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#if defined(CONFIG_CLOCK_STM32_PLL_SRC_HSI)
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pllinit->PLLDiv = LL_RCC_PLLSOURCE_HSI;
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#else
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/*
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* PLL DIV
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* 1 -> LL_RCC_PLLSOURCE_HSE_DIV_1 -> 0x00010000
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* 2 -> LL_RCC_PLLSOURCE_HSE_DIV_2 -> 0x00010001
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* 3 -> LL_RCC_PLLSOURCE_HSE_DIV_3 -> 0x00010002
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* ...
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* 16 -> LL_RCC_PLLSOURCE_HSE_DIV_16 -> 0x0001000F
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*/
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pllinit->PLLDiv = (RCC_CFGR_PLLSRC_HSE_PREDIV |
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(CONFIG_CLOCK_STM32_PLL_PREDIV1 - 1));
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#endif /* CONFIG_CLOCK_STM32_PLL_SRC_HSI */
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#else
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/*
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* PLL Prediv
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* 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
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* 2 -> LL_RCC_PREDIV_DIV_2 -> 0x00000001
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* 3 -> LL_RCC_PREDIV_DIV_3 -> 0x00000002
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* ...
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* 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
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*/
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pllinit->Prediv = CONFIG_CLOCK_STM32_PLL_PREDIV - 1;
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#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
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}
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#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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/* Nothing for now */
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}
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/**
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* @brief Function kept for driver genericity
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*/
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void LL_RCC_MSI_Disable(void)
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{
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/* Do nothing */
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}
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