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https://github.com/zephyrproject-rtos/zephyr
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8206ed42ec
The two redundant SPI dependencies are from 'source'ing a file within an
'if SPI' and then adding another 'depends on SPI' within it.
'if FOO' is just shorthand for adding depends on FOO to each item within
the 'if'. There are no "conditional includes" in Kconfig, so 'if FOO'
has no special meaning around a source. Conditional includes wouldn't be
possible, because an if condition could include (directly or indirectly)
forward references to symbols not defined yet.
Tip: When adding a symbol, check its dependencies in the menuconfig
('ninja menuconfig', then / to jump to the symbol). The menuconfig also
shows how the file with the symbol got included, so if you see
duplicated dependencies, it's easy to hunt down where they come from.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
138 lines
2.8 KiB
Plaintext
138 lines
2.8 KiB
Plaintext
# Kconfig.dw - DesignWare SPI driver configuration options
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#
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#
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# Copyright (c) 2015-2016 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config HAS_SPI_DW
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bool
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help
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Signifies whether DesignWare SPI compatible HW is available
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menuconfig SPI_DW
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bool "Designware SPI controller driver"
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depends on HAS_SPI_DW
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help
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Enable support for Designware's SPI controllers.
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if SPI_DW
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config SPI_DW_ARC_AUX_REGS
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bool "Registers are part of ARC auxiliary registers"
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depends on ARC
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default y
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help
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SPI IP block registers are part of user extended auxiliary
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registers and thus their access is different than memory
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mapped registers.
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config SPI_DW_FIFO_DEPTH
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int "RX and TX FIFO Depth"
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help
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Corresponds to the SSI_TX_FIFO_DEPTH and
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SSI_RX_FIFO_DEPTH of the DesignWare Synchronous
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Serial Interface. Depth ranges from 2-256.
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if SPI_0
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config SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE
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bool "Single interrupt line for all interrupts"
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default y
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help
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Only one line is used to trigger interrupts: RX, TX and ERROR
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interrupt go all through that line, undifferentiated.
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config SPI_DW_PORT_0_CLOCK_GATE
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bool "Enable clock gating"
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depends on CLOCK_CONTROL
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if SPI_DW_PORT_0_CLOCK_GATE
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config SPI_DW_PORT_0_CLOCK_GATE_DRV_NAME
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string
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config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS
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int "Clock controller's subsystem"
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endif # SPI_DW_PORT_0_CLOCK_GATE
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endif # SPI_0
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if SPI_1
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config SPI_DW_PORT_1_INTERRUPT_SINGLE_LINE
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bool "Single interrupt line for all interrupts"
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default y
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config SPI_DW_PORT_1_CLOCK_GATE
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bool "Enable clock gating"
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depends on CLOCK_CONTROL
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if SPI_DW_PORT_1_CLOCK_GATE
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config SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME
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string
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config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS
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int "Clock controller's subsystem"
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endif # SPI_DW_PORT_1_CLOCK_GATE
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endif # SPI_1
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if SPI_2
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config SPI_DW_PORT_2_INTERRUPT_SINGLE_LINE
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bool "Single interrupt line for all interrupts"
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default y
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help
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Only one line is used to trigger interrupts: RX, TX and ERROR
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interrupt go all through that line, undifferentiated.
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config SPI_DW_PORT_2_CLOCK_GATE
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bool "Enable clock gating"
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depends on CLOCK_CONTROL
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if SPI_DW_PORT_2_CLOCK_GATE
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config SPI_DW_PORT_2_CLOCK_GATE_DRV_NAME
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string
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default ""
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config SPI_DW_PORT_2_CLOCK_GATE_SUBSYS
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int "Clock controller's subsystem"
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endif # SPI_DW_PORT_2_CLOCK_GATE
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endif # SPI_2
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if SPI_3
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config SPI_DW_PORT_3_INTERRUPT_SINGLE_LINE
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bool "Single interrupt line for all interrupts"
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default y
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help
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Only one line is used to trigger interrupts: RX, TX and ERROR
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interrupt go all through that line, undifferentiated.
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config SPI_DW_PORT_3_CLOCK_GATE
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bool "Enable clock gating"
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depends on CLOCK_CONTROL
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if SPI_DW_PORT_3_CLOCK_GATE
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config SPI_DW_PORT_3_CLOCK_GATE_DRV_NAME
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string
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default ""
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config SPI_DW_PORT_3_CLOCK_GATE_SUBSYS
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int "Clock controller's subsystem"
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endif # SPI_DW_PORT_3_CLOCK_GATE
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endif # SPI_3
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endif # SPI_DW
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