zephyr/drivers/timer/xlnx_psttc_timer.c
Tomasz Bursztyka 4dcfb5531c isr: Normalize usage of device instance through ISR
The goal of this patch is to replace the 'void *' parameter by 'struct
device *' if they use such variable or just 'const void *' on all
relevant ISRs

This will avoid not-so-nice const qualifier tweaks when device instances
will be constant.

Note that only the ISR passed to IRQ_CONNECT are of interest here.

In order to do so, the script fix_isr.py below is necessary:

from pathlib import Path
import subprocess
import pickle
import mmap
import sys
import re
import os

cocci_template = """
@r_fix_isr_0
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
 ...
(
 const struct device *D = (const struct device *)P;
|
 const struct device *D = P;
)
 ...
}

@r_fix_isr_1
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
 ...
 const struct device *D;
 ...
(
 D = (const struct device *)P;
|
 D = P;
)
 ...
}

@r_fix_isr_2
@
type ret_type;
identifier A;
@@
-ret_type <!fn!>(void *A)
+ret_type <!fn!>(const void *A)
{
 ...
}

@r_fix_isr_3
@
const struct device *D;
@@
-<!fn!>((void *)D);
+<!fn!>(D);

@r_fix_isr_4
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
 ...
(
-const struct device *D = (const struct device *)P;
|
-const struct device *D = P;
)
 ...
}

@r_fix_isr_5
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
 ...
-const struct device *D;
...
(
-D = (const struct device *)P;
|
-D = P;
)
 ...
}
"""

def find_isr(fn):
    db = []
    data = None
    start = 0

    try:
        with open(fn, 'r+') as f:
            data = str(mmap.mmap(f.fileno(), 0).read())
    except Exception as e:
        return db

    while True:
        isr = ""
        irq = data.find('IRQ_CONNECT', start)
        while irq > -1:
            p = 1
            arg = 1
            p_o = data.find('(', irq)
            if p_o < 0:
                irq = -1
                break;

            pos = p_o + 1

            while p > 0:
                if data[pos] == ')':
                    p -= 1
                elif data[pos] == '(':
                    p += 1
                elif data[pos] == ',' and p == 1:
                    arg += 1

                if arg == 3:
                    isr += data[pos]

                pos += 1

            isr = isr.strip(',\\n\\t ')
            if isr not in db and len(isr) > 0:
                db.append(isr)

            start = pos
            break

        if irq < 0:
            break

    return db

def patch_isr(fn, isr_list):
    if len(isr_list) <= 0:
        return

    for isr in isr_list:
        tmplt = cocci_template.replace('<!fn!>', isr)
        with open('/tmp/isr_fix.cocci', 'w') as f:
            f.write(tmplt)

        cmd = ['spatch', '--sp-file', '/tmp/isr_fix.cocci', '--in-place', fn]

        subprocess.run(cmd)

def process_files(path):
    if path.is_file() and path.suffix in ['.h', '.c']:
        p = str(path.parent) + '/' + path.name
        isr_list = find_isr(p)
        patch_isr(p, isr_list)
    elif path.is_dir():
        for p in path.iterdir():
            process_files(p)

if len(sys.argv) < 2:
    print("You need to provide a dir/file path")
    sys.exit(1)

process_files(Path(sys.argv[1]))

And is run: ./fix_isr.py <zephyr root directory>

Finally, some files needed manual fixes such.

Fixes #27399

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-09-02 13:48:13 +02:00

197 lines
5.2 KiB
C

/*
* Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
* Copyright (c) 2018 Xilinx, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT xlnx_ttcps
#include <soc.h>
#include <drivers/timer/system_timer.h>
#include "xlnx_psttc_timer_priv.h"
#define TIMER_INDEX CONFIG_XLNX_PSTTC_TIMER_INDEX
#define TIMER_IRQ DT_INST_IRQN(0)
#define TIMER_BASE_ADDR DT_INST_REG_ADDR(0)
#define TIMER_CLOCK_FREQUECY DT_INST_PROP(0, clock_frequency)
#define TICKS_PER_SEC CONFIG_SYS_CLOCK_TICKS_PER_SEC
#define CYCLES_PER_SEC TIMER_CLOCK_FREQUECY
#define CYCLES_PER_TICK (CYCLES_PER_SEC / TICKS_PER_SEC)
/*
* CYCLES_NEXT_MIN must be large enough to ensure that the timer does not miss
* interrupts. This value was conservatively set using the trial and error
* method, and there is room for improvement.
*/
#define CYCLES_NEXT_MIN (10000)
#define CYCLES_NEXT_MAX (XTTC_MAX_INTERVAL_COUNT)
BUILD_ASSERT(TIMER_CLOCK_FREQUECY ==
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
"Configured system timer frequency does not match the TTC "
"clock frequency in the device tree");
BUILD_ASSERT(CYCLES_PER_SEC >= TICKS_PER_SEC,
"Timer clock frequency must be greater than the system tick "
"frequency");
BUILD_ASSERT((CYCLES_PER_SEC % TICKS_PER_SEC) == 0,
"Timer clock frequency is not divisible by the system tick "
"frequency");
#ifdef CONFIG_TICKLESS_KERNEL
static uint32_t last_cycles;
#endif
static uint32_t read_count(void)
{
/* Read current counter value */
return sys_read32(TIMER_BASE_ADDR + XTTCPS_COUNT_VALUE_OFFSET);
}
static void update_match(uint32_t cycles, uint32_t match)
{
uint32_t delta = match - cycles;
/* Ensure that the match value meets the minimum timing requirements */
if (delta < CYCLES_NEXT_MIN) {
match += CYCLES_NEXT_MIN - delta;
}
/* Write counter match value for interrupt generation */
sys_write32(match, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET);
}
static void ttc_isr(const void *arg)
{
uint32_t cycles;
uint32_t ticks;
ARG_UNUSED(arg);
/* Acknowledge interrupt */
sys_read32(TIMER_BASE_ADDR + XTTCPS_ISR_OFFSET);
/* Read counter value */
cycles = read_count();
#ifdef CONFIG_TICKLESS_KERNEL
/* Calculate the number of ticks since last announcement */
ticks = (cycles - last_cycles) / CYCLES_PER_TICK;
/* Update last cycles count */
last_cycles = cycles;
#else
/* Update counter match value for the next interrupt */
update_match(cycles, cycles + CYCLES_PER_TICK);
/* Advance tick count by 1 */
ticks = 1;
#endif
/* Announce to the kernel*/
z_clock_announce(ticks);
}
int z_clock_driver_init(const struct device *device)
{
uint32_t reg_val;
/* Stop timer */
sys_write32(XTTCPS_CNT_CNTRL_DIS_MASK,
TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
#ifdef CONFIG_TICKLESS_KERNEL
/* Initialise internal states */
last_cycles = 0;
#endif
/* Initialise timer registers */
sys_write32(XTTCPS_CNT_CNTRL_RESET_VALUE,
TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
sys_write32(0, TIMER_BASE_ADDR + XTTCPS_CLK_CNTRL_OFFSET);
sys_write32(0, TIMER_BASE_ADDR + XTTCPS_INTERVAL_VAL_OFFSET);
sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET);
sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_1_OFFSET);
sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_2_OFFSET);
sys_write32(0, TIMER_BASE_ADDR + XTTCPS_IER_OFFSET);
sys_write32(XTTCPS_IXR_ALL_MASK, TIMER_BASE_ADDR + XTTCPS_ISR_OFFSET);
/* Reset counter value */
reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
reg_val |= XTTCPS_CNT_CNTRL_RST_MASK;
sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
/* Set match mode */
reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
reg_val |= XTTCPS_CNT_CNTRL_MATCH_MASK;
sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
/* Set initial timeout */
reg_val = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
CYCLES_NEXT_MAX : CYCLES_PER_TICK;
sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET);
/* Connect timer interrupt */
IRQ_CONNECT(TIMER_IRQ, 0, ttc_isr, 0, 0);
irq_enable(TIMER_IRQ);
/* Enable timer interrupt */
reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_IER_OFFSET);
reg_val |= XTTCPS_IXR_MATCH_0_MASK;
sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_IER_OFFSET);
/* Start timer */
reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
reg_val &= (~XTTCPS_CNT_CNTRL_DIS_MASK);
sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
return 0;
}
void z_clock_set_timeout(int32_t ticks, bool idle)
{
#ifdef CONFIG_TICKLESS_KERNEL
uint32_t cycles;
uint32_t next_cycles;
/* Read counter value */
cycles = read_count();
/* Calculate timeout counter value */
if (ticks == K_TICKS_FOREVER) {
next_cycles = cycles + CYCLES_NEXT_MAX;
} else {
next_cycles = cycles + ((uint32_t)ticks * CYCLES_PER_TICK);
}
/* Set match value for the next interrupt */
update_match(cycles, next_cycles);
#endif
}
uint32_t z_clock_elapsed(void)
{
#ifdef CONFIG_TICKLESS_KERNEL
uint32_t cycles;
/* Read counter value */
cycles = read_count();
/* Return the number of ticks since last announcement */
return (cycles - last_cycles) / CYCLES_PER_TICK;
#else
/* Always return 0 for tickful operation */
return 0;
#endif
}
uint32_t z_timer_cycle_get_32(void)
{
/* Return the current counter value */
return read_count();
}