mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-10 14:01:56 +00:00
9b2fdace1d
Previously, 'USART_WCH_IRQ_HANDLER' used 'DT_INST_IRQ(index, priority)', which incorrectly referenced 'index' instead of 'idx'. This issue went undetected because 'IRQ_CONNECT' drops the priority value on all boards supported by this driver. Fix by using 'DT_INST_IRQ(idx, priority)'. Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
343 lines
9.8 KiB
C
343 lines
9.8 KiB
C
/*
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* Copyright (c) 2024 Google LLC.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT wch_usart
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#include <errno.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/irq.h>
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#include <ch32fun.h>
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struct usart_wch_config {
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USART_TypeDef *regs;
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const struct device *clock_dev;
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uint32_t current_speed;
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uint8_t parity;
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uint8_t clock_id;
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const struct pinctrl_dev_config *pin_cfg;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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void (*irq_config_func)(const struct device *dev);
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#endif
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};
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struct usart_wch_data {
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uart_irq_callback_user_data_t cb;
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void *user_data;
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};
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static int usart_wch_init(const struct device *dev)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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uint32_t ctlr1 = USART_CTLR1_TE | USART_CTLR1_RE | USART_CTLR1_UE;
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uint32_t clock_rate;
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clock_control_subsys_t clock_sys = (clock_control_subsys_t *)(uintptr_t)config->clock_id;
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uint32_t divn;
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int err;
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clock_control_on(config->clock_dev, clock_sys);
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err = clock_control_get_rate(config->clock_dev, clock_sys, &clock_rate);
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if (err != 0) {
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return err;
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}
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divn = (clock_rate + config->current_speed / 2) / config->current_speed;
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switch (config->parity) {
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case UART_CFG_PARITY_NONE:
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break;
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case UART_CFG_PARITY_ODD:
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ctlr1 |= USART_CTLR1_PCE | USART_CTLR1_PS;
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break;
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case UART_CFG_PARITY_EVEN:
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ctlr1 |= USART_CTLR1_PCE;
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break;
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default:
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return -EINVAL;
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}
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regs->BRR = divn;
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regs->CTLR1 = ctlr1;
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regs->CTLR2 = 0;
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regs->CTLR3 = 0;
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err = pinctrl_apply_state(config->pin_cfg, PINCTRL_STATE_DEFAULT);
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if (err != 0) {
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return err;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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config->irq_config_func(dev);
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#endif
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return 0;
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}
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static int usart_wch_poll_in(const struct device *dev, unsigned char *ch)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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if ((regs->STATR & USART_STATR_RXNE) == 0) {
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return -1;
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}
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*ch = regs->DATAR;
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return 0;
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}
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static void usart_wch_poll_out(const struct device *dev, unsigned char ch)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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while ((regs->STATR & USART_STATR_TXE) == 0) {
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}
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regs->DATAR = ch;
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}
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static int usart_wch_err_check(const struct device *dev)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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uint32_t statr = regs->STATR;
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enum uart_rx_stop_reason errors = 0;
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if ((statr & USART_STATR_PE) != 0) {
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errors |= UART_ERROR_PARITY;
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}
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if ((statr & USART_STATR_LBD) != 0) {
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errors |= UART_BREAK;
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}
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if ((statr & USART_STATR_FE) != 0) {
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errors |= UART_ERROR_FRAMING;
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}
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if ((statr & USART_STATR_NE) != 0) {
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errors |= UART_ERROR_NOISE;
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}
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if ((statr & USART_STATR_ORE) != 0) {
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errors |= UART_ERROR_OVERRUN;
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}
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return errors;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static void usart_wch_isr(const struct device *dev)
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{
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struct usart_wch_data *data = dev->data;
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if (data->cb) {
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data->cb(dev, data->user_data);
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}
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}
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static int usart_wch_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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if (!len || !(regs->STATR & USART_STATR_TXE)) {
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return 0;
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}
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regs->DATAR = tx_data[0];
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return 1;
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}
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static int usart_wch_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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if (!size || !(regs->STATR & USART_STATR_RXNE)) {
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return 0;
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}
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rx_data[0] = regs->DATAR;
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return 1;
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}
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static void usart_wch_irq_tx_enable(const struct device *dev)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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regs->CTLR1 |= (USART_CTLR1_TXEIE | USART_CTLR1_TCIE);
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}
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static void usart_wch_irq_tx_disable(const struct device *dev)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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regs->CTLR1 &= ~(USART_CTLR1_TXEIE | USART_CTLR1_TCIE);
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}
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static int usart_wch_irq_tx_ready(const struct device *dev)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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return (regs->STATR & USART_STATR_TXE) > 0;
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}
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static void usart_wch_irq_rx_enable(const struct device *dev)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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regs->CTLR1 |= USART_CTLR1_RXNEIE;
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}
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static void usart_wch_irq_rx_disable(const struct device *dev)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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regs->CTLR1 &= ~USART_CTLR1_RXNEIE;
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}
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static int usart_wch_irq_tx_complete(const struct device *dev)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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return (regs->STATR & USART_STATR_TC) > 0;
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}
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static int usart_wch_irq_rx_ready(const struct device *dev)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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return (regs->STATR & USART_STATR_RXNE) > 0;
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}
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static void usart_wch_irq_err_enable(const struct device *dev)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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regs->CTLR1 |= USART_CTLR1_PEIE;
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regs->CTLR2 |= USART_CTLR2_LBDIE;
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regs->CTLR3 |= USART_CTLR3_EIE;
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}
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static void usart_wch_irq_err_disable(const struct device *dev)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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regs->CTLR1 &= ~USART_CTLR1_PEIE;
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regs->CTLR2 &= ~USART_CTLR2_LBDIE;
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regs->CTLR3 &= ~USART_CTLR3_EIE;
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}
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static int usart_wch_irq_is_pending(const struct device *dev)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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uint16_t ctlr1 = regs->CTLR1;
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uint16_t ctlr2 = regs->CTLR2;
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uint16_t ctlr3 = regs->CTLR3;
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uint16_t statr = regs->STATR;
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uint16_t stat_mask = 0;
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stat_mask |= (ctlr1 & USART_CTLR1_TXEIE) ? USART_STATR_TXE : 0;
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stat_mask |= (ctlr1 & USART_CTLR1_TCIE) ? USART_STATR_TC : 0;
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stat_mask |= (ctlr1 & USART_CTLR1_RXNEIE) ? USART_STATR_RXNE | USART_STATR_ORE : 0;
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stat_mask |= (ctlr1 & USART_CTLR1_IDLEIE) ? USART_STATR_IDLE : 0;
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stat_mask |= (ctlr1 & USART_CTLR1_PEIE) ? USART_STATR_PE : 0;
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stat_mask |= (ctlr2 & USART_CTLR2_LBDIE) ? USART_STATR_LBD : 0;
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stat_mask |=
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(ctlr3 & USART_CTLR3_EIE) ? USART_STATR_NE | USART_STATR_ORE | USART_STATR_FE : 0;
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stat_mask |= (ctlr3 & USART_CTLR3_CTSIE) ? USART_STATR_CTS : 0;
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return (statr & stat_mask) > 0;
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}
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static int usart_wch_irq_update(const struct device *dev)
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{
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return 1;
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}
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static void usart_wch_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
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void *user_data)
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{
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struct usart_wch_data *data = dev->data;
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data->cb = cb;
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data->user_data = user_data;
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}
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#endif /*CONFIG_UART_INTERRUPT_DRIVEN*/
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static DEVICE_API(uart, usart_wch_driver_api) = {
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.poll_in = usart_wch_poll_in,
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.poll_out = usart_wch_poll_out,
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.err_check = usart_wch_err_check,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = usart_wch_fifo_fill,
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.fifo_read = usart_wch_fifo_read,
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.irq_tx_enable = usart_wch_irq_tx_enable,
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.irq_tx_disable = usart_wch_irq_tx_disable,
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.irq_tx_ready = usart_wch_irq_tx_ready,
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.irq_rx_enable = usart_wch_irq_rx_enable,
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.irq_rx_disable = usart_wch_irq_rx_disable,
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.irq_tx_complete = usart_wch_irq_tx_complete,
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.irq_rx_ready = usart_wch_irq_rx_ready,
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.irq_err_enable = usart_wch_irq_err_enable,
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.irq_err_disable = usart_wch_irq_err_disable,
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.irq_is_pending = usart_wch_irq_is_pending,
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.irq_update = usart_wch_irq_update,
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.irq_callback_set = usart_wch_irq_callback_set,
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#endif
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};
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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#define USART_WCH_IRQ_HANDLER_DECL(idx) \
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static void usart_wch_irq_config_func_##idx(const struct device *dev);
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#define USART_WCH_IRQ_HANDLER_FUNC(idx) .irq_config_func = usart_wch_irq_config_func_##idx,
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#define USART_WCH_IRQ_HANDLER(idx) \
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static void usart_wch_irq_config_func_##idx(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority), usart_wch_isr, \
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DEVICE_DT_INST_GET(idx), 0); \
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irq_enable(DT_INST_IRQN(idx)); \
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}
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#else
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#define USART_WCH_IRQ_HANDLER_DECL(idx)
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#define USART_WCH_IRQ_HANDLER_FUNC(idx)
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#define USART_WCH_IRQ_HANDLER(idx)
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#endif
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#define USART_WCH_INIT(idx) \
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PINCTRL_DT_INST_DEFINE(idx); \
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USART_WCH_IRQ_HANDLER_DECL(idx) \
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static struct usart_wch_data usart_wch_##idx##_data; \
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static const struct usart_wch_config usart_wch_##idx##_config = { \
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.regs = (USART_TypeDef *)DT_INST_REG_ADDR(idx), \
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.current_speed = DT_INST_PROP(idx, current_speed), \
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.parity = DT_INST_ENUM_IDX(idx, parity), \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
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.clock_id = DT_INST_CLOCKS_CELL(idx, id), \
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.pin_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
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USART_WCH_IRQ_HANDLER_FUNC(idx)}; \
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DEVICE_DT_INST_DEFINE(idx, &usart_wch_init, NULL, &usart_wch_##idx##_data, \
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&usart_wch_##idx##_config, PRE_KERNEL_1, \
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CONFIG_SERIAL_INIT_PRIORITY, &usart_wch_driver_api); \
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USART_WCH_IRQ_HANDLER(idx)
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DT_INST_FOREACH_STATUS_OKAY(USART_WCH_INIT)
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