Andrew Boie e34f1cee06 x86: implement kernel page table isolation ... Implement a set of per-cpu trampoline stacks which all interrupts and exceptions will initially land on, and also as an intermediate stack for privilege changes as we need some stack space to swap page tables. Set up the special trampoline page which contains all the trampoline stacks, TSS, and GDT. This page needs to be present in the user page tables or interrupts don't work. CPU exceptions, with KPTI turned on, are treated as interrupts and not traps so that we have IRQs locked on exception entry. Add some additional macros for defining IDT entries. Add special handling of locore text/rodata sections when creating user mode page tables on x86-64. Restore qemu_x86_64 to use KPTI, and remove restrictions on enabling user mode on x86-64. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>		2020-01-17 16:17:39 -05:00
..
arc	dts: Rename generated_dts_board*.{h,conf} to devicetree*.{h,conf}	2020-01-17 17:57:59 +01:00
arm	dts: Rename generated_dts_board*.{h,conf} to devicetree*.{h,conf}	2020-01-17 17:57:59 +01:00
common
nios2	dts: Rename generated_dts_board*.{h,conf} to devicetree*.{h,conf}	2020-01-17 17:57:59 +01:00
posix	dts: Rename generated_dts_board*.{h,conf} to devicetree*.{h,conf}	2020-01-17 17:57:59 +01:00
riscv	dts: Rename generated_dts_board*.{h,conf} to devicetree*.{h,conf}	2020-01-17 17:57:59 +01:00
x86	x86: implement kernel page table isolation	2020-01-17 16:17:39 -05:00
xtensa	dts: Rename generated_dts_board*.{h,conf} to devicetree*.{h,conf}	2020-01-17 17:57:59 +01:00
arch_inlines.h
cpu.h
syscall.h