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https://github.com/zephyrproject-rtos/zephyr
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f7dd9856ba
This patch is almost entirely aesthetics, designed to isolate the variant configurations to a simple macro API (just IN/OUT), reduce complexity derived from code pasted out of the larger ns16550 driver, and keep the complexity out of the (very simple!) core code. Useful when hacking on the driver in contexts where it isn't working yet. The sole behavioral change here is that I've removed the runtime printk hook installation in favor of defining an arch_printk_char_out() function which overrides the weak-linked default (that is, we don't need to install a hook, we can be the default hook at startup). Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
90 lines
2.6 KiB
C
90 lines
2.6 KiB
C
/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <sys/util.h>
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#include <drivers/pcie/pcie.h>
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#include <soc.h>
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/* Legacy I/O Port Access to a NS16550 UART */
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#ifdef UART_NS16550_ACCESS_IOPORT
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#define IN(reg) sys_in8(reg + UART_NS16550_ACCESS_IOPORT)
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#define OUT(reg, val) sys_out8(val, reg + UART_NS16550_ACCESS_IOPORT)
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#endif
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/* "Modern" mapping of a UART into a PCI MMIO device. The registers
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* are still bytes, but spaced at a 32 bit stride instead of packed
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* together.
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*/
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#ifdef X86_SOC_EARLY_SERIAL_PCIDEV
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static uintptr_t pci_bar;
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#define IN(reg) (sys_read32(pci_bar + reg * 4) & 0xff)
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#define OUT(reg, val) sys_write32((val) & 0xff, pci_bar + reg * 4)
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#endif
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/* Still other devices use a MMIO region containing packed byte
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* registers
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*/
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#ifdef X86_SOC_EARLY_SERIAL_MMIO8_ADDR
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#define IN(reg) sys_read8(X86_SOC_EARLY_SERIAL_MMIO8_ADDR + reg)
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#define OUT(reg, val) sys_write8(val, X86_SOC_EARLY_SERIAL_MMIO8_ADDR + reg)
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#endif
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#define REG_THR 0x00 /* Transmitter holding reg. */
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#define REG_IER 0x01 /* Interrupt enable reg. */
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#define REG_FCR 0x02 /* FIFO control reg. */
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#define REG_LCR 0x03 /* Line control reg. */
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#define REG_MCR 0x04 /* Modem control reg. */
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#define REG_LSR 0x05 /* Line status reg. */
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#define REG_BRDL 0x00 /* Baud rate divisor (LSB) */
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#define REG_BRDH 0x01 /* Baud rate divisor (MSB) */
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#define IER_DISABLE 0x00
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#define LCR_8N1 (BIT(0) | BIT(1))
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#define LCR_DLAB_SELECT BIT(7)
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#define MCR_DTR BIT(0)
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#define MCR_RTS BIT(1)
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#define LSR_THRE BIT(5)
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#define FCR_FIFO BIT(0) /* enable XMIT and RCVR FIFO */
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#define FCR_RCVRCLR BIT(1) /* clear RCVR FIFO */
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#define FCR_XMITCLR BIT(2) /* clear XMIT FIFO */
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#define FCR_FIFO_1 0 /* 1 byte in RCVR FIFO */
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static void serout(int c)
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{
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while ((IN(REG_LSR) & LSR_THRE) == 0) {
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}
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OUT(REG_THR, c);
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}
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int arch_printk_char_out(int c)
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{
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if (c == '\n') {
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serout('\r');
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}
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serout(c);
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return c;
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}
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void z_x86_early_serial_init(void)
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{
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#ifdef X86_SOC_EARLY_SERIAL_PCIDEV
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pci_bar = pcie_get_mbar(X86_SOC_EARLY_SERIAL_PCIDEV, 0);
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pcie_set_cmd(X86_SOC_EARLY_SERIAL_PCIDEV, PCIE_CONF_CMDSTAT_MEM, true);
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#endif
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OUT(REG_IER, IER_DISABLE); /* Disable interrupts */
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OUT(REG_LCR, LCR_DLAB_SELECT); /* DLAB select */
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OUT(REG_BRDL, 1); /* Baud divisor = 1 */
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OUT(REG_BRDH, 0);
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OUT(REG_LCR, LCR_8N1); /* LCR = 8n1 + DLAB off */
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OUT(REG_MCR, MCR_DTR | MCR_RTS);
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/* Turn on FIFO. Some hardware needs this before transmitting */
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OUT(REG_FCR, FCR_FIFO | FCR_FIFO_1 | FCR_RCVRCLR | FCR_XMITCLR);
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}
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