mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-02 11:12:59 +00:00
82a08a7678
According to RM, when increasing the CPU frequency, the new number of wait states to the Flash latency bits must be written and verified before modifying the CPU clock source and/or the CPU clock prescaler, to prevent NMI to occur; when decreasing the CPU frequency, after. Tested with STM32L462 SOC and MSI with several frequencies, both increasing and decreasing. HSE built, not tested. Signed-off-by: Giancarlo Stasi <giancarlo.stasi@nexxiot.com> |
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| .. | ||
| beetle_clock_control.c | ||
| clock_control_esp32.c | ||
| clock_control_esp32.h | ||
| clock_control_mcux_ccm.c | ||
| clock_control_mcux_mcg.c | ||
| clock_control_mcux_pcc.c | ||
| clock_control_mcux_scg.c | ||
| clock_control_mcux_sim.c | ||
| clock_control_rv32m1_pcc.c | ||
| clock_stm32_ll_common.c | ||
| clock_stm32_ll_common.h | ||
| clock_stm32_ll_h7.c | ||
| clock_stm32_ll_mp1.c | ||
| clock_stm32f1.c | ||
| clock_stm32f2_f4_f7.c | ||
| clock_stm32f0_f3.c | ||
| clock_stm32g4.c | ||
| clock_stm32g0.c | ||
| clock_stm32l4_l5_wb.c | ||
| clock_stm32l0_l1.c | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Kconfig.beetle | ||
| Kconfig.esp32 | ||
| Kconfig.mcux_ccm | ||
| Kconfig.mcux_mcg | ||
| Kconfig.mcux_pcc | ||
| Kconfig.mcux_scg | ||
| Kconfig.mcux_sim | ||
| Kconfig.nrf | ||
| Kconfig.rv32m1 | ||
| Kconfig.stm32 | ||
| Kconfig.stm32f1 | ||
| Kconfig.stm32f2_f4_f7 | ||
| Kconfig.stm32f0_f3 | ||
| Kconfig.stm32g0 | ||
| Kconfig.stm32g4 | ||
| Kconfig.stm32h7 | ||
| Kconfig.stm32l4_l5_wb | ||
| Kconfig.stm32l0_l1 | ||
| nrf_clock_calibration.c | ||
| nrf_clock_calibration.h | ||
| nrf_power_clock.c | ||