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https://github.com/zephyrproject-rtos/zephyr
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07160fa153
SPARC is an open and royalty free processor architecture. This commit provides SPARC architecture support to Zephyr. It is compatible with the SPARC V8 specification and the SPARC ABI and is independent of processor implementation. Functionality specific to SPRAC processor implementations should go in soc/sparc. One example is the LEON3 SOC which is part of this patch set. The architecture port is fully SPARC ABI compatible, including trap handlers and interrupt context. Number of implemented register windows can be configured. Some SPARC V8 processors borrow the CASA (compare-and-swap) atomic instructions from SPARC V9. An option has been defined in the architecture port to forward the corresponding code-generation option to the compiler. Stack size related config options have been defined in sparc/Kconfig to match the SPARC ABI. Co-authored-by: Nikolaus Huber <nikolaus.huber.melk@gmail.com> Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
41 lines
1.1 KiB
C
41 lines
1.1 KiB
C
/*
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* Copyright (c) 2019-2020 Cobham Gaisler AB
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_SPARC_SPARC_H_
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#define ZEPHYR_INCLUDE_ARCH_SPARC_SPARC_H_
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/*
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* @file
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* @brief Definitions for the SPARC V8 architecture.
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*/
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/* Processor State Register */
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#define PSR_VER_BIT 24
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#define PSR_PIL_BIT 8
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#define PSR_VER (0xf << PSR_VER_BIT)
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#define PSR_EF (1 << 12)
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#define PSR_S (1 << 7)
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#define PSR_PS (1 << 6)
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#define PSR_ET (1 << 5)
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#define PSR_PIL (0xf << PSR_PIL_BIT)
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#define PSR_CWP 0x1f
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/* Trap Base Register */
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#define TBR_TT_BIT 4
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#define TBR_TBA 0xfffff000
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#define TBR_TT 0x00000ff0
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/* Trap types in TBR.TT */
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#define TT_RESET 0x00
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#define TT_WINDOW_OVERFLOW 0x05
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#define TT_WINDOW_UNDERFLOW 0x06
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#define TT_DATA_ACCESS_EXCEPTION 0x09
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#endif /* ZEPHYR_INCLUDE_ARCH_SPARC_SPARC_H_ */
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