mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-07 07:02:52 +00:00
6e8775ff84
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an undesirable API for the following reasons: - it's inconsistent with the rest of the DT_NODE_HAS_FOO names - DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand for macros which are equivalent to DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) && - DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck - DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway - it is seen as a somewhat aesthetically challenged name Replace all users with DT_NODE_HAS_STATUS(..., okay), which is semantically equivalent. This is mostly done with sed, but a few remaining cases were done by hand, along with whitespace, docs, and comment changes. These special cases include the Nordic SOC static assert files. Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
206 lines
6.2 KiB
C
206 lines
6.2 KiB
C
/*
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* Copyright (c) 2018, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include <soc.h>
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#include <dt-bindings/rdc/imx_rdc.h>
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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#include "wdog_imx.h"
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/* Initialize Resource Domain Controller. */
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static void SOC_RdcInit(void)
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{
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/* Move M4 core to the configured RDC domain */
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RDC_SetDomainID(RDC, rdcMdaM4, M4_DOMAIN_ID, false);
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/* Set access to WDOG3 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapWdog3,
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RDC_DOMAIN_PERM(M4_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
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false, false);
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
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/* Set access to UART_1 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapUart1, RDC_DT_VAL(uart1), false, false);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
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/* Set access to UART_2 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapUart2, RDC_DT_VAL(uart2), false, false);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart3), okay)
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/* Set access to UART_3 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapUart3, RDC_DT_VAL(uart3), false, false);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart4), okay)
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/* Set access to UART_4 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapUart4, RDC_DT_VAL(uart4), false, false);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart5), okay)
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/* Set access to UART_5 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapUart5, RDC_DT_VAL(uart5), false, false);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart6), okay)
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/* Set access to UART_6 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapUart6, RDC_DT_VAL(uart6), false, false);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
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/* Set access to GPIO_1 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapGpio1, RDC_DT_VAL(gpio1), false, false);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
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/* Set access to GPIO_2 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapGpio2, RDC_DT_VAL(gpio2), false, false);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay)
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/* Set access to GPIO_3 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapGpio3, RDC_DT_VAL(gpio3), false, false);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay)
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/* Set access to GPIO_4 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapGpio4, RDC_DT_VAL(gpio4), false, false);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay)
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/* Set access to GPIO_5 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapGpio5, RDC_DT_VAL(gpio5), false, false);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio6), okay)
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/* Set access to GPIO_6 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapGpio6, RDC_DT_VAL(gpio6), false, false);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio7), okay)
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/* Set access to GPIO_7 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapGpio7, RDC_DT_VAL(gpio7), false, false);
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#endif
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#ifdef CONFIG_IPM_IMX
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/* Set access to MU B for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapMuB, RDC_DT_VAL(mub), false, false);
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#endif /* CONFIG_IPM_IMX */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(epit1), okay)
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/* Set access to EPIT_1 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapEpit1, RDC_DT_VAL(epit1), false, false);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(epit2), okay)
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/* Set access to EPIT_2 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapEpit2, RDC_DT_VAL(epit2), false, false);
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#endif
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}
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/* Initialize cache. */
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static void SOC_CacheInit(void)
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{
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/* Enable System Bus Cache */
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/* set command to invalidate all ways and write GO bit
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* to initiate command
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*/
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LMEM_PSCCR = LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK;
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LMEM_PSCCR |= LMEM_PSCCR_GO_MASK;
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/* Wait until the command completes */
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while (LMEM_PSCCR & LMEM_PSCCR_GO_MASK)
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;
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/* Enable system bus cache, enable write buffer */
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LMEM_PSCCR = (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK);
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__ISB();
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/* Enable Code Bus Cache */
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/* set command to invalidate all ways and write GO bit
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* to initiate command
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*/
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LMEM_PCCCR = LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
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LMEM_PCCCR |= LMEM_PCCCR_GO_MASK;
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/* Wait until the command completes */
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while (LMEM_PCCCR & LMEM_PCCCR_GO_MASK)
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;
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/* Enable code bus cache, enable write buffer */
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LMEM_PCCCR = (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
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__ISB();
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__DSB();
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}
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/* Initialize clock. */
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static void SOC_ClockInit(void)
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{
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/* OSC/PLL is already initialized by Cortex-A9 core */
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/* Enable IP bridge and IO mux clock */
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CCM_ControlGate(CCM, ccmCcgrGateIomuxIptClkIo, ccmClockNeededAll);
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CCM_ControlGate(CCM, ccmCcgrGateIpmux1Clk, ccmClockNeededAll);
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CCM_ControlGate(CCM, ccmCcgrGateIpmux2Clk, ccmClockNeededAll);
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CCM_ControlGate(CCM, ccmCcgrGateIpmux3Clk, ccmClockNeededAll);
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#ifdef CONFIG_UART_IMX
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/* Set UART clock is derived from OSC clock (24M) */
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CCM_SetRootMux(CCM, ccmRootUartClkSel, ccmRootmuxUartClkOsc24m);
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/* Configure UART divider */
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CCM_SetRootDivider(CCM, ccmRootUartClkPodf, 0);
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/* Enable UART clock */
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CCM_ControlGate(CCM, ccmCcgrGateUartClk, ccmClockNeededAll);
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CCM_ControlGate(CCM, ccmCcgrGateUartSerialClk, ccmClockNeededAll);
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#endif /* CONFIG_UART_IMX */
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#ifdef CONFIG_COUNTER_IMX_EPIT
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/* Select EPIT clock is derived from OSC (24M) */
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CCM_SetRootMux(CCM, ccmRootPerclkClkSel, ccmRootmuxPerclkClkOsc24m);
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/* Configure EPIT divider */
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CCM_SetRootDivider(CCM, ccmRootPerclkPodf, 0);
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/* Enable EPIT clocks */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(epit1), okay)
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CCM_ControlGate(CCM, ccmCcgrGateEpit1Clk, ccmClockNeededAll);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(epit2), okay)
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CCM_ControlGate(CCM, ccmCcgrGateEpit2Clk, ccmClockNeededAll);
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#endif
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#endif /* CONFIG_COUNTER_IMX_EPIT */
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}
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/**
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*
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* @brief Perform basic hardware initialization
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*
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* Initialize the interrupt controller device drivers.
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* Also initialize the counter device driver, if required.
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*
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* @return 0
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*/
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static int mcimx6x_m4_init(struct device *arg)
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{
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ARG_UNUSED(arg);
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unsigned int oldLevel; /* Old interrupt lock level */
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/* Disable interrupts */
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oldLevel = irq_lock();
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/* Configure RDC */
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SOC_RdcInit();
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/* Disable WDOG3 powerdown */
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WDOG_DisablePowerdown(WDOG3);
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/* Initialize Cache */
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SOC_CacheInit();
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/* Initialize clock */
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SOC_ClockInit();
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/*
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* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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/* Restore interrupt state */
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irq_unlock(oldLevel);
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return 0;
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}
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SYS_INIT(mcimx6x_m4_init, PRE_KERNEL_1, 0);
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