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https://github.com/zephyrproject-rtos/zephyr
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feae3249b2
Adds the necessary bits to initialize TLS in the stack area and sets up CPU registers during context switch. Register g7 is used to point to the thread data. Thread data is accessed with negative offsets from g7. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com> |
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| .. | ||
| arc | ||
| arm | ||
| common | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| arch_inlines.h | ||
| cpu.h | ||
| syscall.h | ||