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https://github.com/zephyrproject-rtos/zephyr
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b9a4e30d3b
Add Clock Control driver support for Renesas RZ/G3S Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com> Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
135 lines
3.0 KiB
C
135 lines
3.0 KiB
C
/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/dt-bindings/clock/renesas_rzg_clock.h>
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#include <zephyr/kernel.h>
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#define DT_DRV_COMPAT renesas_rz_cpg
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static int clock_control_renesas_rz_on(const struct device *dev, clock_control_subsys_t sys)
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{
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if (!dev || !sys) {
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return -EINVAL;
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}
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uint32_t *clock_id = (uint32_t *)sys;
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uint32_t ip = (*clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT;
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uint32_t ch = (*clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT;
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switch (ip) {
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case RZ_IP_GTM:
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R_BSP_MODULE_START(FSP_IP_GTM, ch);
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break;
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case RZ_IP_GPT:
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R_BSP_MODULE_START(FSP_IP_GPT, ch);
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break;
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case RZ_IP_SCIF:
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R_BSP_MODULE_START(FSP_IP_SCIF, ch);
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break;
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case RZ_IP_RIIC:
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R_BSP_MODULE_START(FSP_IP_RIIC, ch);
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break;
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case RZ_IP_RSPI:
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R_BSP_MODULE_START(FSP_IP_RSPI, ch);
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break;
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case RZ_IP_MHU:
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R_BSP_MODULE_START(FSP_IP_MHU, ch);
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break;
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case RZ_IP_DMAC:
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R_BSP_MODULE_START(FSP_IP_DMAC, ch);
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break;
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case RZ_IP_CANFD:
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R_BSP_MODULE_START(FSP_IP_CANFD, ch);
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break;
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case RZ_IP_ADC:
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R_BSP_MODULE_START(FSP_IP_ADC, ch);
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break;
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default:
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return -EINVAL; /* Invalid FSP IP Module */
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}
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return 0;
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}
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static int clock_control_renesas_rz_off(const struct device *dev, clock_control_subsys_t sys)
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{
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if (!dev || !sys) {
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return -EINVAL;
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}
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uint32_t *clock_id = (uint32_t *)sys;
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uint32_t ip = (*clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT;
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uint32_t ch = (*clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT;
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switch (ip) {
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case RZ_IP_GTM:
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R_BSP_MODULE_STOP(FSP_IP_GTM, ch);
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break;
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case RZ_IP_GPT:
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R_BSP_MODULE_STOP(FSP_IP_GPT, ch);
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break;
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case RZ_IP_SCIF:
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R_BSP_MODULE_STOP(FSP_IP_SCIF, ch);
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break;
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case RZ_IP_RIIC:
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R_BSP_MODULE_STOP(FSP_IP_RIIC, ch);
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break;
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case RZ_IP_RSPI:
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R_BSP_MODULE_STOP(FSP_IP_RSPI, ch);
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break;
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case RZ_IP_MHU:
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R_BSP_MODULE_STOP(FSP_IP_MHU, ch);
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break;
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case RZ_IP_DMAC:
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R_BSP_MODULE_STOP(FSP_IP_DMAC, ch);
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break;
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case RZ_IP_CANFD:
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R_BSP_MODULE_STOP(FSP_IP_CANFD, ch);
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break;
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case RZ_IP_ADC:
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R_BSP_MODULE_STOP(FSP_IP_ADC, ch);
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break;
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default:
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return -EINVAL; /* Invalid */
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}
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return 0;
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}
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static int clock_control_renesas_rz_get_rate(const struct device *dev, clock_control_subsys_t sys,
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uint32_t *rate)
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{
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if (!dev || !sys || !rate) {
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return -EINVAL;
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}
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uint32_t *clock_id = (uint32_t *)sys;
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fsp_priv_clock_t clk_src = (*clock_id & RZ_CLOCK_MASK) >> RZ_CLOCK_SHIFT;
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uint32_t clk_div = (*clock_id & RZ_CLOCK_DIV_MASK) >> RZ_CLOCK_DIV_SHIFT;
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uint32_t clk_hz = R_FSP_SystemClockHzGet(clk_src);
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*rate = clk_hz / clk_div;
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return 0;
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}
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static DEVICE_API(clock_control, rz_clock_control_driver_api) = {
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.on = clock_control_renesas_rz_on,
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.off = clock_control_renesas_rz_off,
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.get_rate = clock_control_renesas_rz_get_rate,
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};
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static int clock_control_rz_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return 0;
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}
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DEVICE_DT_INST_DEFINE(0, clock_control_rz_init, NULL, NULL, NULL, PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &rz_clock_control_driver_api);
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