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https://github.com/zephyrproject-rtos/zephyr
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d49cc8a56f
This serves two main purposes: - change the CPU clock via devicetree nodes - provide the APB frequency to device drivers via the clock driver interface Theoretically this could also support choosing between the available clock sources, but right now we only support LPOSC0 going into PLL0, going into AHB. Turning the PLL back off is also not supported since the only current use case is to set the PLL frequency, turn it on, and switch the AHB over to it. Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
19 lines
422 B
Plaintext
19 lines
422 B
Plaintext
# Copyright (c) 2024 GARDENA GmbH
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#
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# SPDX-License-Identifier: Apache-2.0
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config CLOCK_CONTROL_SI32_PLL
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bool "SI32 PLL clock control"
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default y
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depends on DT_HAS_SILABS_SI32_PLL_ENABLED
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config CLOCK_CONTROL_SI32_AHB
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bool "SI32 AHB clock control"
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default y
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depends on DT_HAS_SILABS_SI32_AHB_ENABLED
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config CLOCK_CONTROL_SI32_APB
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bool "SI32 APB clock control"
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default y
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depends on DT_HAS_SILABS_SI32_APB_ENABLED
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