Short explanation of remote wake up:
The device has a possibility to wake up the HOST by sending
the wake up request. The request must be previously
explicitly enabled by the HOST just before the SUSPEND.
The HOST enables the remote wake up functionality by sending
SET_FEATURE request with remote wake up flag set to 1.
This ususally happens just before the device is suspended.
About this PR:
When the device decides to wake up the HOST it sends proper request.
Nordic USB HW is creating an event when the request has been sent.
The Zephyr USB device stack must proerly react to this event and
change the state of the device from SUSPENDED. For example if the
device was previously in CONFIGURED state it will remain CONFIGURED.
For state changes refer to Chapter 9.1.1 form USB 2.0 specification.
Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
- nRF21540 Front End Module Development Kit board definition
- nRF52840 MCU definitions based on nRF52840 Devkit files
Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
Expose the internal JESD216 function used to read data from the SFDP
region, and another function to read the JEDEC ID.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Some flash drivers are capable of issuing a JESD216 READ_SFDP command
to read serial flash discoverable parameters. Allow applications and
utilities access to API that reads the JEDEC ID from those devices.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Some flash drivers are capable of issuing a JESD216 READ_SFDP command
to read serial flash discoverable parameters. Allow applications and
utilities access to that capability where it's supported.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
This commit reworks the SPI NOR driver to be more flexible in how
flash device configuration is obtained. Three alternatives are
supported:
* MINIMAL takes only the flash size from devicetree. The erase sizes
are hard-coded to the traditionally supported instructures.
* DEVICETREE requires that the data from the device's JESD216 Basic
Flash Parameters table be provided through devicetree. This
supports multiple page sizes and erase configurations, and lays a
foundation for significant enhancements in the future including
4-byte address, sleeping while waiting for operation completion, and
other features that are described by JESD216 parameters.
* RUNTIME requires nothing from the devicetree node, instead reading
the Basic Flash Parameters from the device at runtime. It extends
DEVICETREE by allowing the same firmware to run on boards with
different flash chips.
For MINIMAL and DEVICETREE the JEDEC ID from the devicetree node is
checked against the value read at runtime to confirm that the device
configuration is accurate.
The default SFDP source is MINIMAL.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Use the new SFDP infrastructure to read the supported erase type sizes
and commands from the Basic Flash Parameters block. This removes the
need for explicit reference to most block sizes from this driver.
We're also seeing devices where the page size is not 256 bytes.
Accommodate them.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
With SFDP support we no longer need to get the JEDEC ID or device size
from devicetree. Make them optional in drivers that have been
converted to support SFDP. When runtime SFDP is not enabled the
presence of the required properties will be verified at build-time.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Allow the devicetree binding for a jedec,spi-nor device to provide the
device capabilities by encoding the Serial Flash Discoverable
Parameters Basic Flash Parameters table in the devicetree node. This
supports applications where a specific flash device will be used and
runtime discovery of device capabilities is not desired.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The spi_nor flash interface was designed for flash devices that use a
standard SPI interface to devices that are compatible with the Micron
M25P80 serial flash, identified in Linux as compatible jedec,spi-nor.
The JEDEC Serial Flash Discoverable Parameters standard (JESD216) was
designed to allow these devices to be self-describing. As we are
increasingly being asked to support flash memories that do not use
"standard" erase sizes or commands we need data structures and helper
functions to extract information about a flash interface at runtime.
For some of these devices the commands hard-coded in the current
implementation are simply wrong.
Define generic structures that support the SFDP hierarchy and the core
Basic Flash Parameters table. The description will also support
SPI-NAND and xSPI devices that conform to the JESD216 standards.
Add bitfield values and helper functions to extract some information
that drivers might need from JESD216 fields. At this time only
information that is likely to be used is extracted; more may be added
in the future.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The one provided in the spi_nor.h header is inappropriate for this
device, which doesn't support be32k. Also that definition is moving
into the spi_nor implementation file.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Removes redundancy on atmel_rf2xx.overlay message. Clarifies supported
variations section and notes about network on index.rst.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The dticks field was changed from a signed to an unsigned
value so now the assert test to ensure it isn't negative
is no longer needed.
fixes#26355
Signed-off-by: David Leach <david.leach@nxp.com>
In the function do_net_init() the paths for ipv6 and ipv4 now use the
same api to determine the source address.
Fixes#27428
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Use anytree module to display tree and to allow easy exporting into
json.
Add option to export results into a json file.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add board support for NXP i.MX8M Mini EVK. This board has the following
features:
Processor : i.MX8M Mini Quad applications processor
Memory : 32-bit LPDDR4 w/2 GB
eMMC 5.0/5.1 w/16 GB
SD/MMC connector
QSPI w/32 MB
Connectivity : MIMO 1x1 Wi-Fi 802.11a/b/g/n/ac and BT4.1
Ethernet
PCIe M.2
USB : 2x USB 3.0 Type C
Debug : JTAG connector
MicroUSB for debug console
More information about this board can be found in NXP website: https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/evaluation-kit-for-thebr-i.mx-8m-mini-applications-processor:8MMINILPD4-EVK
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Add IUART driver based on MCUX SDK. This driver is used to provide
serial console support on i.MX8M Mini SoC.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
RDC module is used by i.MX8MM SoC, so let's create a Kconfig symbol
which will be used to enable the module in SDK.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Add support for the Cortex-M1 ARM DesignStart FPGA reference design
running on the Digilent Arty development board.
This board uses IRQ 7 (the last IRQ) as a level-detect non-interrupt
signal to determine whether the V2C-DAPLINK shield is installed. This
IRQ line is always pending when the shield is not installed. Use IRQ 6
instead.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add board definition for the ARM DesignStart FPGA Cortex-M1 reference
design on the Digilent Arty FPGA development board.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add devicetree bindings for the Xilinx AXI GPIO v2 IP. This GPIO
controller has an optional "GPIO2" port, which is not always present.
The Xilinx specific devicetree property names and their meaning match a
subset of what can automatically be generated based on the FPGA logic
design using https://github.com/Xilinx/device-tree-xlnx. These
properties are also used by the Linux kernel.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Change the documentation for the arm,dtcm (Data Tightly Coupled Memory)
to reflect that it is not specific to the Cortex-M7 (but also present
on e.g. the Cortex-M1).
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add support for the Cortex-M1 ARM DesignStart FPGA SoC. This is not an
SoC in the traditional sense but more of a base to build an SoC upon.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
The Wait For Interrupt (WFI) instruction ARM Cortex-M1 CPU does not
operate as a powersave instruction. It is always executed as a NOP.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
The Data Tightly Coupled Memory (DTCM) of the Cortex-M1 present in the
Cortex-M1 ARM DesignStart FPGA implementation is No-Execute (NX), so
__ramfunc linked in the DTCM will cause a hard fault when executed.
Use the Xilinx Block RAM (bram0) present in the reference design for
demonstrating __ramfunc instead.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Extend check to determine a usable ARM NVIC IRQ line to verify that the
IRQ line is not always pending.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
