The Cortex-M0(+) and in general processors that support only the ARMv6-M
instruction set have a reduced set of registers and fields compared to
the ARMv7-M compliant processors.
This change goes through all core registers and disables or removes
everything that is not part of the ARMv6-M architecture when compiling
for Cortex-M0.
Jira: ZEP-1497
Change-id: I13e2637bb730e69d02f2a5ee687038dc69ad28a8
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Cortex-M0(+) and in general processors that support only the ARMv6-M
instruction set can only access the NVIC_IPRn registers with word
accesses, and not with byte ones like the Cortex-M3 and onwards. This
patch addresses the issue by modifying the way that _NvicIrqPrioSet()
writes to the IPRn register, using a word access for Cortex-M0(+).
A similar issue is addressed for internal exceptions, this time for the
SHPR registers that are accessed differently on ARMv6-M.
Reference code taken from CMSIS.
Jira: ZEP-1497
Change-id: I08e1bf60b3b70579b42f4ab926ee835c18bb65bb
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Since the value is treated as uint8_t internally anyway, just use
uint8_t for the input and output parameter types.
Jira: ZEP-1497
Change-Id: I61d68eb39cba5d82dad6ab7593b267c26e003d2b
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
That module is not used anymore: it was introduced pre-Zephyr to add
some kind of awareness when debugging ARM Cortex-M3 code with GDB but
was never really used by anyone. It has bitrotted, and with the recent
move of the tTCS and tNANO data structures to common _kernel and
k_thread, it does not even compile anymore.
Jira: ZEP-1284, ZEP-951
Change-Id: Ic9afed00f4229324fe5d2aa97dc6f1c935953244
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
nano_cpu_idle/nano_cpu_atomic_idle were not ported to the unified
kernel, and only the old APIs were available. There was no real impact
since, in the unified kernel, only the idle thread should really be
doing power management. However, with a single-threaded kernel, these
functions can be useful again.
The kernel internals now make use of these APIs instead of the legacy
ones.
Change-Id: Ie8a6396ba378d3ddda27b8dd32fa4711bf53eb36
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The Cortex-M3/4 kernel was reserving priorities 0 and 1 for itself, but
was not registering any exception on priority 0. Only reserve priority 0
and use it for SVC and fault exceptions instead of priority 1.
Change-Id: Iff2405e27fd4bed4e49ab90ec2ae984f2c0a83a6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
There are now three flags that decide how many priorities are reserved
by the kernel, each one requiring one priority level: Zero Latency
Interrupts, BASEPRI locking (for SVC usage) and faults that are not at
priority -1, so that taking them in an ISR actually triggers the fault
synchronously.
Change-Id: I7f4d760c9110051aeb82dcfd8cd68026a9b74b54
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This allows using it in _EXC_PRIO() instead of hardcoding 2 and 3.
Change-Id: I3549be54602643e06823ba63beb6a6992f39f776
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Move interrupt initialization for the ARC to its own
device. The init function for the arc will be only
doing platform specific operations
Jira: ZEP-1288
Change-Id: Icb04c3622890021c65cd24cecf6cafee6c37caf9
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
Drop the unnecessary trailing whitespace formatting in inline asm.
Change-Id: I351df91b7175fe21d268d325865838b4840def8d
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Replace the use of a hardwired temporary register in the irq_lock()
implementation with a local variable. This will allow the compiler
more flexibility in register allocation.
Change-Id: Ifbdb52fca1d40404d55934343ac2a8153df7e1a8
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The cortex-m4 irq_lock() implementation uses a movs instruction, thus
clobbering the condition code, but does not include the clobber in the
asm clobber list. This is a bug in the situation where the compiler
schedules a live condition code over the inline lock instructions.
Since the irq_lock() implementation does not need to kill the CC we
simply switch to mov from movs.
Take the opportunity to drop the unnecessay .n and let the assembler
choose an appropriate encoding.
This fixes a bug found by inspection, it has not actually been
observed in real code.
Change-Id: Id60fa3362df9d4bf05c3d5e23066410ede92d73c
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Memory accesses could be reordered before an irq_lock() or
after an irq_unlock() without the memory barriers.
See commit 15bc537712 for the
ARM fix for a complete description of the issue and fix.
Change-Id: I1d96fe0088d90150f0888c2893d017155fc0a0a7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Memory accesses could be reordered before an irq_lock() or after an
irq_unlock() without the memory barriers.
See commit 15bc537712 for the ARM fix for
a complete description of the issue and fix.
Change-Id: I056afb0406cabe0e1ce2612904e727ccce5f6308
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Memory accesses could be reordered before an irq_lock() or after an
irq_unlock() without the memory barriers.
See commit 15bc537712 for the ARM fix for
a complete description of the issue and fix.
Change-Id: Ic92a6b33f62a938d2252d68eccc55a5fb07c9114
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Add the missing memory clobber to irq_unlock() in order to prevent the
compiler reordering memory operations over the unlock.
Change-Id: If1d664079796618ed247ff5b33b8b3f85fb7e680
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The inline asm definition of irq_lock() on the ARM architecture marks
the ASM as volatile which prevents the compiler from removing the
isntruction but does provide any information to the compiler to
prevent the inline ASM instruction being re-ordered relative to other
instructions. The instruction used in irq_lock() do not touch memory,
however in order to acheive their intended purpose they must be
ordered relative to other memory access instruction. This is acheived
by adding the "memory" clobber.
Instances of the compiler inappropriately re-ordering irq_lock() calls
relative to other instructions without this patch can be observed in
the code generated for k_sleep() on NRF51 target boards.
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Change-Id: I9d42d54cd9a50e8150c10ce6715af7ca2f5cfe51
If a particular project needs to add additional data to the
binary image, in most cases the entire linker script needs to
forked into the project space, causing maintenance issues if
the main linker script is changed.
Now we add some Kconfig options to allow a project to specify
some additional linker scripts which get included by the main
one in a few key areas:
1) In the definition to the 'rodata' section, which can allow
additional data to be included in this ROM section.
2) In the definition to the 'datas' section, which allows
additional data to be included in this RAM section.
3) Arbitrary additional sections to be included at the end of
the binary.
For 1 and 2, this is useful to include data generated outside of
the normal C compilation, such as data structures that are created
by special build tools.
3 is useful for including arbitrary binary blobs inside the final
image, such as for peripheral or co-processor firmware.
Change-Id: I5738d3d6da25f5bc96cda8ae806bf1a3fb34bd5d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Sets the interrupt descriptor table in C domain.
Change-Id: Ia8d2f585ebf60464aeedf2a54363e4683cf257a5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The pointer value needs to be dereferenced first.
Change-Id: I80d8a9b4837adfc7d0efc69c229c863d05e52a93
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It is referred to as D/B in the Intel manuals.
Change-Id: If021d875da2d83a256926d9233f1559c8c2ed1db
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Zephyr kernel is unable to compile when CONFIG_RUNTIME_NMI is enabled in
defconfig on ARM's architectures.
This patch addresses the following issues:
* In nmi.c _DefaultHandler() is referencing a function
(_ScbSystemReset()) not defined in Zephyr. This has now been replaced
with sys_arch_reboot.
* nmi.h is included in ASM files and due to the usage of "extern" the
compilation ends with an error. Added the directive _ASMLANGUAGE to
prevent the problem.
Jira: ZEP-1319
Change-Id: I7623ca97523cde04e4c6db40dc332d93ca801928
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Most kernel APIs are now ready for inclusion in the API guide.
The APIs largely follow a standard template to provide users
of the API guide with a consistent look-and-feel.
Change-Id: Ib682c31f912e19f5f6d8545d74c5f675b1741058
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Add Low Power States support to the power shim layer
and show the usage in the quark_se sample.
States are defined as follow:
- SYS_POWER_STATE_CPU_LPS: SS2 with LPSS enabled
- SYS_POWER_STATE_CPU_LPS_1: SS2 with LPSS disabled
- SYS_POWER_STATE_CPU_LPS_2: SS1 with LPSS disabled
Jira: ZEP-994
Change-Id: Ie4b93f6e539cb53fc035be00280b66b2cb0d9fea
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
Updates x86 floating point support to reflect changes that have
been made in recent months.
* Many, many, many cosmetic changes (mostly revisions to comments).
* Elimination of unnecessary function aliases that were needed
to support the task and fiber versions of certain APIs.
* Elimination of run-time code to enable a thread's "FP regs"
option bit if the "SSE regs" option bit was set. The kernel
now recognizes that the thread is using the FPU as long as
either option bit is set. (If the thread has both option bits
enabled this is the same as if only the "SSE regs" bit is set.)
Change-Id: Ic12abc54b6fa78921749b546d8debf23e7ad232d
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
C++ support moved from nanokernel.h to kernel.h.
Change-Id: I5e1631941e26f4ab3f311b680267b743bab15e40
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Symbols now use the K_ prefix which is now standard for the
unified kernel. Legacy support for these symbols is retained
to allow existing applications to build successfully.
Change-Id: I3ff12c96f729b535eecc940502892cbaa52526b6
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
There are a number of data sections that are repeated across
all the linker scripts for various architecture. In practice these
don't always get updated and we have had problems with bit-rot.
Consolidate these to make maintenance easier.
x86 linker scripts now follow the same naming convention and we
get rid of a linker-epilog.h that wasn't necessary and whose purpose
has been lost to the mists of time. If applications want to define their
own sections they should be allowed to. Linker scripts for x86 do not
end with .h any more, they are not C header files even though we use
C's preprocessor.
Issue: ZEP-688
Change-Id: I893eb4619969695c1f980efd7c2ec9fa5dad136d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
All M7 features common to M3/M4 are working. New features like Tightly
Coupled Memory (TCM) are not yet supported.
Change-Id: I5f7b292e70843aec415728f24c973bb003014f4b
Jira: ZEP-977
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
Support Cortex-M0, M3/M4, M7 is easier when the memory map is defined in
terms of absolute addresses.
Based work from: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
Change-Id: I860860c369e8bed6c6c23661a15ce464d87ff221
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
With this patch we introduce unified kernel support for NIOS II.
Not all test cases have been ported, but the following command
currently succeeds with 43/43 passing test cases:
$ sanitycheck --arch=nios2 -xKERNEL_TYPE=unified \
--tag=unified_capable
Issue: ZEP-934
Change-Id: Id8effa0369a6a22c4d0a789fa2a8e108af0e0786
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
ARC does not align data structures by 4 bytes by default.
Add necessary linker sections.
Change-Id: I3bf7aa38b9bc8cba56f824469040c027968fa564
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Not disabling SysTick as it is optional by the spec.
SVC not used as there is no priority-based interrupt masking (only
PendSV is used).
Largely based on a previous work done by Euan Mutch <euan@abelon.com>.
Jira: ZEP-783
Change-Id: I38e29bfcf0624c1aea5f9fd7a74230faa1b59e8b
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
This is used by a test case, and it's better to just put this
here instead of forking the linker scripts.
Change-Id: Ifbb90b73bb26118ae2422cc6feccb3db58a26f2c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This mechanism was intended to reserve space during the first pass for
certain data structures created by gen_idt, but this is unnecessary.
The only memory addresses that must be fixed between the two passes are the
locations of the interrupt stubs, which are in the .text section much
earlier than the generated data structures; they do not shift.
Change-Id: I3aab00e171e6a9ff439a7af8d69769e4c29337a7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
For XIP images, in order to avoid the situation when
__data_rom_start is 32-bit aligned, but the actual data is placed
after rodata section, which may not end exactly at 32-bit border,
pad rodata section, so __data_rom_start points at data and it is
32-bit aligned.
On non-XIP images this may enlarge image size up to 3 bytes.
This is generally not an issue, since modern ROM and FLASH
memory is usually 4k aligned.
Change-Id: I3d37fccbc610615585d776144ab9e281368258d6
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
ARC interrupts can be either level or pulse.
Level interrupts remain asserted until the interrupt service routine
clears the interrupt at the peripheral. This is the default and most
common case.
Pulse interrupts have an extra flip-flop that converts a pulse to a
level. The ARC auto-clears this level as the interrupt service routine
is entered. As such, an interrupt handler for a pulse interrupt need
not clear the interrupt.
It is the rare device that uses pulse interrupts.
Nothing currently calls this inline function so ARC interrupts are
LEVEL by default.
(see ZEP-83)
Change-Id: I09ef86aae1926c1327e82ff99c2f8aa7eabde684
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Binutils ld has an annoying misfeature (apparently a regression from a
few years ago) that alignment directives (and alignment specifiers on
symbols) apply only to the runtime addresses and not, apparently, to
the load address region specified with the "AT>" syntax. The net
result is that by default the LMA output ends up too small for the
addresses generated in RAM. See here for some details:
https://sourceware.org/ml/binutils/2013-06/msg00246.htmlhttps://sourceware.org/ml/binutils/2014-01/msg00350.html
The required workaround/fix is that AFAICT any section which can have
inherit a separate VMA vs. LMA from a previous section must specify an
"ALIGN_WITH_INPUT" attribute. Otherwise the sections will get out of
sync and the XIP data will be wrong at runtime.
No, I don't know why this isn't the default behavior.
A further complexity is that this feature only works as advertised
when the section is declared with the "AT> region" syntax after the
block and not "AT(address)" in the header. If you use the header
syntax (with or without ALIGN_WITH_INPUT), ld appears to DOUBLE-apply
padding and the LMA ends up to big. This is almost certainly a
binutils bug, but it's trivial to work around (and the working syntax
is actually cleaner) so we adjust the usage here.
Note finally that this patch includes an effective reversion of commit
d82e9dd9 ("x86: HACK force alignment for _k_task_list section"), which
was an earlier workaround for what seems to be the same issue.
Jira: ZEP-955
Change-Id: I2accd92901cb61fb546658b87d6752c1cd14de3a
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Interrupt stubs now just push the ISR and parameter onto the stack
and jump to the common interrupt code, never to return.
Change-Id: I82543d8148b5c7dfe116c43f41791f852614bb28
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Merge the Cortex-M3/M4 memory map bits into the master memory map in
prep for it being shared with Cortex-M7 support and Cortex-M0 support
going forward.
Change-Id: I211fc2a2d7d49082b51463f06e6e71cca75d886f
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Due to the memory pool structure only static declaration of
memory pool is possible.
Change-Id: I4797ed88fd2ac3b7812ff26e552e1745611c4575
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
