Add workaround to HFCLK start and stop in nrf54l. In future workaround
will be in nrfx driver.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add option to set the lowest DVFS operation point during initialization.
Option is by default enabled for nrf54h cores with DVFS.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Deprecate NRFS_LOCAL_DOMAIN_DVFS_SCALE_DOWN_AFTER_INIT option for
scaling down CPU frequency during dvfs handler initialization.
Clock control API is managing access to DVFS and DVFS should not
be controlled bypassing this API. Deprecated feature will be added in
the clock control.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Factorize STM32_CLOCK_*_GET() and STM32_MCO_CFGR_*_GET() macros
into a single series of STM32_DT_CLKSEL_*_GET() macros based on
recently introduced new common macros STM32_DT_CLKSEL_*_SHIFT and
STM32_DT_CLKSEL_*_MASK.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add Clock Control driver support for Renesas RZ/G3S
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This driver is mostly the initial seed for further implementation of a
real clock driver.
It doesn't allow the user to choose the clock source for the various
peripherals. The driver hardcodes some sane values.
Note that for now, the driver snps,designware-i2c does not support
"clocks" attribute. So this patch hardcode the clock configuration in
the init of the clock driver.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
clean up usage of usage "#ifdef STM32_SRC_SYSCLK"
and code under the "#else" from clock_stm32_ll_common.c.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
Some stm32f4, like the sm32f411 mcu have clk 48M on the main PLL output q
Some stm32f4, like the sm32f412 mcu have clk 48M on the PLL I2S output q
This PR is for selecting the right one
Signed-off-by: Francois Ramu <francois.ramu@st.com>
- Add a condition to check the clock supplying the CPU to match with
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
- Correct CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for EK-RA4W1
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
Remove the LL_RCC_PLLI2S_ConfigDomain_48M for the stm32f4
w/o Q divider on the PLLI2S to configure the PLL48CK
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Check that the plli2s has a DIV-Q output or not. That depends
on the PLLi2S of some stm32F4xx devices
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes a multitude of Kconfigs that wrongly appear on devices
where support is literally impossible
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Makes the esp_console_init() calling during hardware initialization
conditioned to CONFIG_ESP_CONSOLE
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
When using synthesized low frequency clock, HFXO should be running
to ensure correct frequency.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
New events from nrfx_clock driver are not utilized for now
by the clock_control, so should be ignored to avoid assertion.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Enables the fractional-N (FRACN) setting for PLL1 in the STM32H5XX
clock driver.
This feature allows achieving a system clock frequency of 250 MHz from
an 8 MHz `clk_hse`.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add support for STM32H757 SoC, which shares its design
with STM32H747 with added cryptography peripherals.
Signed-off-by: Grzegorz Runc <g.runc@grinn-global.com>
Unlike the RP2040, the RP2350 has multiple tick generators that need to
be started. Start TIMER0 and TIMER1 tick generators during
clock_control_init.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Add support for SoC-specific clock ids and update the initialization
function to support the existing RP2040 and add support for the RP2350.
clock_control_rpi_pico.c uses numerical values for clock ids taken from
rpi_pico_clock.h which are the "clock generator". For the RP2350 these
values are different for some of the same logical clock sources, as well
as the RP2040 and RP2350 having different clock sources available.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
This is a follow-up to commit fe0e2dbc60.
If `nrf_clock_control_request_sync()` ends up with a timeout, before
returning it must cancel the request that was not fulfilled on time.
Otherwise, the request may actually finish successfully a bit later,
but the caller will not be aware that the clock needs to be released
(since the call resulted in an error). And actually even more serious
problem is that because the `req` structure is placed on stack, after
the function returns, the contents of this structure will be probably
overwritten with some other data, so if the request finishes at that
point, an attempt to execute the callback function pointed by this
structure will most likely cause a crash.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The clock_stm32_ll_common.c function set_up_plls calls
LL_RCC_PLL_Disable();and it was not waiting for the
disable to complete before trying to configure
the pll sysclock which creates a race condition for
pll configuration.The wait for re-enabling the RCC pll
is already there, it was just missing the wait for
the disable before configuration. Also added the wait for PLL2.
Signed-off-by: Benjamin Curtis Byers <ben.byers@ubcobikes.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
There were redundant code in full_irq_lock(), full_irq_unlock()
functions that supposed to be used when ZLI IRQs are disabled.
These functions are compiled in only when CONFIG_ZERO_LATENCY_IRQS
is set, hence the non-ZLI execution path was never included
in final binaries.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
The nrf-hsfll was previously the only supported HSFLL clock, hence it
was not namespaced fully. Since we added nrf-hsfll-global, we should
add the namespace to nrf-hsfll as well.
Updates drivers and devicetree uses of HSFLL as well.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The clock controller/manager registers are updated with
the correct divider values by bootloader via hand-off
data, so now we can use the clock controller to get the
clock value of each peripheral during the run time.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Add a function to compute the clock48 from the clock tree
of a stm32f412/f413 mcu. The value depends on its clock source
Requires to identify the PLL source HSE or HSI.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the configuration of the PLL Q divider of main PLL
and I2S_Q of the PLLI2S toset the PLL48MHz clock which feeds
the USB, SDMMC, RNG through the RCC_DCKCFGR2 register.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Implement the zero latency interrupt safe APIs to the HFXO clock
commonly used by the bluetooth stach from zero latency interrupt
context.
Co-authored-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
