When a GPIO pin is configured, the shim driver will first read the
current values in the controller registers to keep the other pins from
changing their configuration. After that it sets the bits for the
corresponding pin accordingly.
When the flag to enable interrupts is passed to the function, the
corresponding bits are all set properly, but no changes are made if
interrupts are not requested. This makes it impossible to disable
interrupts for a given pin once they've been enabled.
Fix it by always resetting the interrupt enabled bit when they have not
been requested. Other values can be left untouched as they won't have
any effect.
Jira: ZEP-1717
Change-Id: I30e97bb06d966291e23d0c66ddf39bce615c287b
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Requesting a flash_write with a length of 0 results in a flash
position being written. Instead we should return 0 unless there is
some other input parameter that is invalid.
Change-Id: Ife6e6e2314bbee2bde7d0b69db3122ca00c361e0
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
We default DTC to /usr/bin/dtc so we can build targets that are using
devicetree and not using the zephyr SDK (which provides a version of
dtc).
Change-Id: I84c3e3181eda75b4da715e16bbde2e67f28785e7
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove tests that assert due to invocation from ISR which is not supported.
Change-Id: Ib2313b8f75db0140aa475281bd76ba0414d6a481
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
Add the HTTPS (HTTP over TLS) server sample application on top
of the current HTTP Parser Library and mbedTLS. This code uses
TLS to stablish a secure connection and HTTP parser to identify
the request and the proper response.
Jira: ZEP-799
Change-Id: Ifbbcd0347bec47d12158440e50a82dc2966334d3
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
Dummy time.h to fulfill the compilations requirements of certain
libraries i.e. mbedTLS
Change-Id: I07e66dbf07337b935dabe9eecdf1be3850bbf394
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
This is a workaround for lack of driver API support for multicast
management. So, instead we want to receive all multicast frames
"by default", or otherwise basic IPv6 features, like address
resolution, don't work. On Kinetis Ethernet controller, that
translates to enabling promiscuous mode. The real fix depends
on ZEP-1673.
Change-Id: I98a27584be65bdc405de005383eb30bad2a7fcfc
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
The dhcpv4 client code builds ip and udp packets from scratch rather
than using the network stack to do the heavy lifting (why ?).
When it computes the udp checksum of each packet it builds it neglects
to clear any preexisting detritus from the checksum field. The result
of this is that some packets will be built with correct checksums and
some will be built with incorrect checksums.
This is the underlying reason that the dhcp client often taken many
retransmissions and elapsed time before in order to acquire an IP
address.
Change-Id: Iebd1ed34e06f7f2e53d45f6d1555e22f48490287
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Fix long standing issue where a dhcpv4 message type is compared
against a dhcpv4 state machine state name rather than a message type.
The issue probably arizes due to the similarity in names between
messages and states. By accident, the relevant message types and
states happen to share the same numbers, hence the implementation
works, but is ill defined.
Change-Id: I5c028de4336ff42f6696e28b3492c932c58b5a05
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Added conf files for qemu_cortex_m3, until a better solution
than CONF_FILE=prj_$(BOARD).conf exists in the makefile.
Change-Id: I1edc4f37bb3c49ecb65abf7c93b3c9f4608d601e
Signed-off-by: Richard Peters <mail@richardpeters.de>
Add basic PHY management sufficient to detect link up, link down and
auto negotiated link speed / duplex. The PHY driver is implemented as
a state machine that executed in the system work queue. The
implementation is non blocking, using the MII interrupt to capture the
completion of read and write events.
This PHY management should be fairly generic. In the future, it may be
beneficial to pull this code out as a standalone PHY driver for use
with other ethernet drivers.
JIRA: ZEP-1674
Change-Id: I3dcb5c14982ef4b40591fcf10d84840b8a2558e5
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Modify the network setup routine to accept the following parameters:
- network context
- accept callback
- server IP address
- server port
This change will allow us to reuse this routine for TLS.
Change-Id: I1fdbaa908783c69f87863cbc597b42f39358762c
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
This patch adds the QEMU prj file for the HTTP server sample
app.
Change-Id: I0b910b5ec9970a7ffe9621e19d9544d899c22132
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
Makes it cleared that zoap_update_from_block() doesn't modify the
packet.
Change-Id: I35429b153370c50eb5ae9c914b47a3144faf2f04
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This fixes the case that a request for block number (NUM) 0, using a
16 byte block was considered invalid.
This was because it is encoded as the value 0 (zero), which can be
expressed as the BLOCK1 option present but without any value
associated. The old code considered this the same as the option not
existing.
Change-Id: I0f3912803a88865e9f544a6d0078ed4231775a88
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Add information about how to run libcoap's[1] implementation of the
ETSI testcases against zoap-server.
Jira: ZEP-1538
[1] https://github.com/obgm/libcoap (branch develop)
Change-Id: I6aa5989575cc15630371aa0761bee98fb6fe1b80
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Now types and functions have better explanations of their usage and
parameters associated.
Jira: ZEP-1657
Change-Id: I146688324080ac3cf0876f1db3c92c9514e1303d
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Added a riscv-privilege.h header file that contains common
definitions for all riscv SOCs supporting the riscv
privileged architecture specification.
This shall ease addition of future riscv SOCs supporting
the riscv privileged architecture spec.
Change-Id: I5714bf70eeda738a25967ed26d3d0d2aaa0c9989
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Its current placement was splitting the vector table in half.
Move to rodata, a better place for it. There's no requirement for
it to be in the text section.
Change-Id: I67724b2a26a9cb62c2ccd473cb54c53e4f74dc32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Replace the hardwired #! python path with a PATH search. This is
necessary to allow build tools to execute from a virtualenv.
Change-Id: Ib83131fd96656bc9f76c606356b1f92c877cc117
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
This was reported by ISSM compiler.
Jira: ZEP-1179
Change-Id: Ib97ed8da830126c9fbfa2269c8b2327d2f1be2f4
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
This was reported by ISSM compiler.
Jira: ZEP-1179
Change-Id: I5700ff6b374815325fa858cfd11f8938c82d8337
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
This was reported by ISSM compiler.
Jira: ZEP-1179
Change-Id: Ib54d43bbfae4c7819b1e2b82d2931bfe1201ecce
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
The BSS section needs to use AT> in XIP systems otherwise the LMA
addresses in the ELF binary are wrong, leading to issues if we
try to manipulate the binary with objcopy. The GROUP_DATA_LINK_IN
macro does the right thing here.
This was already done on other arches but ARC was missed.
Change-Id: I93748e919e0b68c1ff2dfb4b85b7064a8d980f3a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
When test GPIO_INT_EDGE, there is no code to skip GPIO_INT_LEVEL
and jump to the end of the function. So GPIO_INT_LEVEL will
always be checked (Besides, it't always true), even if it's
testing GPIO_INT_EDGE, which will cause GPIO_INT_EDGE cases fail.
Add a goto statement for GPIO_INT_EDGE to skip GPIO_INT_LEVEL.
Jira: ZEP-1685
Change-Id: I10ce21c04c49f34aafdc2cd2f60f3e5377d6f1f5
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
This test case uses PWM0 port to test PWM on Quark Se.
However PWM0 port on Quark D2000 is initialized as tdo,
not PWM0 and disabling tdo will kill JTAG on D2000. So
use PWM1 and add PINMUX setting code to configure PIN_24
as PWM1 port, then the case will work on D2000 board.
Change-Id: Ib28d4750dac7396529388b781fb64bde048139d6
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
the commit test below adc driver api with different resolutions
and modes
adc_enable()
adc_read()
adc_disable()
move original adc test to adc_simple folder
Change-Id: I016b5e67a5d89fc8d5ae76f33799e5d3eb3e1cf8
Signed-off-by: jing wang <jing.j.wang@intel.com>
Remove tests that assert due to invocation from ISR which is not supported.
Change-Id: Idd2360847a467af6afdd9fbed8f87a620d9ed2f7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The current I2C API provides inline functions to access 1 byte
register addresses. This commit adds a set of I2C inline functions
as shortcuts to handle:
- 16 bit register addressing. A family of functions that allows to
handle 2 byte register addressing and can receive the address
parameter as a simple variable. This allows a developer to handle
the address as a C constant or macro.
- Multiple byte addressing. A family of functions to access
registers with a configurable register address size. This family
of functions handle register addressing of any size but receives
the address parameter as a byte array.
Change-Id: Id369ab9eaad7eea807554371d3a520f67dc2e0f2
Signed-off-by: Juan Manuel Cruz Alcaraz <juan.m.cruz.alcaraz@intel.com>
