Add basic driver for GIC V3 interrupt controller.
This implementation supports
- distributor, re-distributor and cpu interface initialization
- configuration and handling of SPI, PPI and SGI.
- V2 Legacy mode is not supported and uses system interface.
Current implementation supports GIC secure state only.
All interrupts are routed to Secure EL1 as 'irq' by configuring
them as Group1 Secure.
TODO:
- MPIDR based affinity routing setting.
- percpu redistributor probe
- message based SPI and SGI generation api
- EL1NS support. Legacy mode support.
- LPI/ITS is not supported.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Convert driver to use new DT_INST macros throughout. This allows us to
also remove dts_fixup.h that are no longer used.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fixing ICFGRn register access with `sys_{read,write}32`
since this register is not byte-accessible.
Type of `val` changed to u32 to match reg width.
Fixes#24339
Supersedes #24422
Signed-off-by: Bartlomiej Flak <flakbartlomiej@gmail.com>
* add interrupt lock in low level API to gurantee the
correctness of operations.
* make some functions as in-line functions
* clean up and optimize the code comments
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Convert older DT_INST_ macro use in litex drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in atmel sam0 drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in sifive drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This adds the per CPU address offset for intel_apl_adsp, so
the correct base address can be calculated under SMP.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The CAVS interrupt controller has different base addresses for
each CPU. When running under SMP, the driver needs to look at
the correct address for the CPU the ISR is running so interrupts
can be dispatched correctly. This adds a function to calculate
the correct base address. Note that each supported SoC may have
different offsets so per SoC config will need to added. Support
for intel_s1000 is added as an example.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The dw_ictl interrupt controller is an interrupt aggregator
supporting multi-level interrupts. Therefore, it needs to be
initialized earlier than any downstream interrupt controllers
and devices.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The cavs_ictl interrupt controller is an interrupt aggregator
supporting multi-level interrupts. Therefore, it needs to be
initialized earlier than any downstream interrupt controllers
and devices.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit fixes the field definition names for `GICD_ICFGR`, which
were incorrectly prefixed with `GICC_`.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The current Generic Interrupt Controller (GIC) driver makes use of the
multi-level interrupt mechanism and `irq_nextlevel` public interface.
This is a less-than-ideal implementation for the following reasons:
1. The GIC is often used as the main interrupt controller for the
Cortex-A and Cortex-R family SoCs and, in this case, it is not a 2nd
level interrupt controller; in fact, it is the root interrupt
controller and therefore should be treated as such.
2. The only reason for using `irq_nextlevel` here is to interface the
architecture implementation to the interrupt controller functions.
Since there is no nesting or multiple instances of an interrupt
controller involved, there is really no point in adding such an
abstraction.
3. 2nd level topology adds many unnecessary abstractions and results
in strange coding artefacts as well as performance penalty due to
additional branching.
This commit refactors the GIC driver interface as follows:
1. Remove the current GIC driver interface based on the multi-level
interrupt mechanism and the `irq_nextlevel` public interface.
2. Define the GIC driver interface in
`include/drivers/interrupt_controller/gic.h` and allow the arch
implementation to directly invoke this interface.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
If IO APIC is in logical destination mode, local APICs compare their
logical APIC ID defined in LDR (Logical Destination Register) with
the destination code sent with the interrupt to determine whether or not
to accept the incoming interrupt.
This patch programs LDR in xAPIC mode to support IO APIC logical mode.
The local APIC ID from local APIC ID register can't be used as the
'logical APIC ID' because LAPIC ID may not be consecutive numbers hence
it makes it impossible for LDR to encode 8 IDs within 8 bits.
This patch chooses 0 for BSP, and for APs, cpu_number which is the index
to x86_cpuboot[], which ultimately assigned in z_smp_init[].
Signed-off-by: Zide Chen <zide.chen@intel.com>
Currently IO APIC is working in physical destination mode, which
doesn't support interrupt to be delivered to multiple local APICs.
By definition only 4 bits [59:63] in IO APIC IOREDTBL register are
available for destination addresses and it contains an APIC ID only.
This patch changes it to logical destination mode so that IOREDTBL
can potentially define a set of processors and it's posible to deliver
interrupts to multiple APICs.
Also it changes delivery mode from fixed to lowest priority. The reason
being in fixed mode, the interrupt could be delivered to all CPUs
which put burden in software to handle repeated interrupts. While in
lowest priority mode, interrupt is delivered to one local APIC only.
Signed-off-by: Zide Chen <zide.chen@intel.com>
During driver rewrite, the field to specify the base address of
the interrupt controller was dropped, which results in error in
device initialization due to accessing random address (or null).
Fix it by specifying the base address.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Same deal as in commit eddd98f811 ("kconfig: Replace some single-symbol
'if's with 'depends on'"), for the remaining cases outside defconfig
files. See that commit for an explanation.
Will do the defconfigs separately in case there are any complaints
there.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
stm32_exti_enable was returning errors on line > 32 or line pointing
to non implemented line. Both conditions are hard-coded, hence there
is no use to detect them dynamically in the code.
Check them with assert. As a consequence, function could now be void.
Additionally, enable exti irq line only if both checks are passed.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Since it is now possible to disable/re-enable interrupts and
also to reconfigure an already configured interrupt, it is
now required to clear non requested triggers.
While it is not strictly requested, triggers are also cleared
when interrupt is disabled (assuming trigger should be configured
when interrupt is enabled).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
fixup exti
Lot of misdefined variables that went in undetected due to lack of CI on
this board. Fix them and test build with new SDK.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
DesignWare driver can manage different amount of irqs so let's make it
configurable via DTS.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Base address does not change at runtime, thus storing it directly into
device's config.
Also keeping it consistent in naming: s/port/dev
And no need to store irq_num as it is unused.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Invalid channel should be filtered in intmux isr, please refer to
page 1243~1244 of chapter 36 INTMUX of RV32M1 RM.
Note: Unlike the NVIC, the INTMUX does not latch pending source
interrupts. This means that the INTMUX output channel ISRs must
check for and handle a 0 value of the CHn_VEC register to account
for spurious interrupts.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
miv already had it defined, but let's shorten the names and use
them in the driver. This also adds it for sifive-freedom.
Signed-off-by: Olof Johansson <olof@lixom.net>
This is no longer needed, since all in-tree platforms are only using
the standard mstatus formats. Remove it to avoid the complexity.
Signed-off-by: Olof Johansson <olof@lixom.net>
The current GIC driver implementation only supports the GIC-400, which
implements the GICv2 interface.
This commit refactors the GIC driver to support multiple GIC versions
and adds GICv1 interface support (GICv1 and GICv2 interfaces are very
similar).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The current GIC configuration scheme is designed to support only one
specific type and version of GIC (i.e. GIC-400 that implements the
GICv2 interface).
This commit adds a set of GIC version configuration symbols that can
be selected by the SoC configuration to specify which version of GIC
interface is implemented in the SoC.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
sam0 and stm32 specific interrupt controller headers are meant to be
public, and as such should be found in
include/drivers/interrupt_controller and not in
drivers/interrupt_controllers.
Fixing documentation issues as well.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
If it is such a thing (a CAVT intc), it will not be targeting Intel
s1000 SoC only. UP squarde ADSP use the same intc. So renaming it to
CAVS. Though CAVS name might be wrong (CAVS being an overall
architecture name, and not an IP block specification).
Reducing the amount of lines by using if/endif as well.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Pattern being <domain>_<model>.<c/h>.
Here interrupt_controller as a domain would be far too long so
shortening it to "intc", as DTS does actually.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Remove leading/trailing blank lines in .c, .h, .py, .rst, .yml, and
.yaml files.
Will avoid failures with the new CI test in
https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only
checks changed files.
Move the 'target-notes' target in boards/xtensa/odroid_go/doc/index.rst
to get rid of the trailing blank line there. It was probably misplaced.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
The GIC-400 driver currently only supports SPIs because the (32) offset
for the INTIDs is hard-coded in the driver. At the driver level there is
no really difference between PPIs and SPIs so we can easily extend the
driver to support PPIs as well.
This is useful if we want to add support for the ARM Generic Timers that
use INTIDs in the PPI range.
SPI interrupts are in the range [0-987]. PPI interrupts are in the range
[0-15].
This commit adds interrupt 'type' cell to the GIC device tree binding
and changes the 'irq' cell to use interrupt type-specific index, rather
than a linear IRQ number.
The 'type'+'irq (index)' combo is automatically fixed up into a linear
IRQ number by the scripts/dts/gen_defines.py script.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add support for the built-in Programmable Interrupt Controller
found in the SweRV EH1 RISC-V CPU
Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
