As we are allowed to pass any integer value as as software
fatal exception reason, we need to fix the inline assembly
for ARMv6-M, to accept large immediate offsets. We do this
by changing the way we write the exception reason to R0.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
include/sys/arch_inlines.h will contain all architecture APIs
that are used by public inline functions and macros,
with implementations deriving from include/arch/cpu.h.
kernel/include/arch_interface.h will contain everything
else, with implementations deriving from
arch/*/include/kernel_arch_func.h.
Instances of duplicate documentation for these APIs have been
removed; implementation details have been left in place.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This patch re-namespaces global variables and functions
that are used only within the arch/arm/ code to be
prefixed with z_arm_.
Some instances of CamelCase have been corrected.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
k_cpu_idle() and k_cpu_atomic_idle() were being directly
implemented by arch code.
Rename these implementations to z_arch_cpu_idle() and
z_arch_cpu_atomic_idle(), and call them from new inline
function definitions in kernel.h.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Various C and Assembly modules
make function calls to z_sys_trace_*. These merely call
corresponding functions sys_trace_*. This commit
is to simplify these by making direct function calls
to the sys_trace_* functions from these modules.
Subsequently, the z_sys_trace_* functions are removed.
Signed-off-by: Mrinal Sen <msen@oticon.com>
Refactor z_arch_is_user_context() for ARM, so it uses
the CMSIS CONTROL_nPRIV_Msk instead of hard-coded 0x1.
Fixing also some typos in include/arch/arm/syscall.h.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
when enable CONFIG_CUSTOM_SECTION_ALIGN, it need less alignment
memory for image rom region. But that needs carefully configure
MPU region and sub-regions(ARMv7-M) to cover this feature.
Fixes: #17337.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Include .gcc_except_table (sub-)sections in linker files to support C++
with exceptions enabled. If these sections are not mapped warnings will
be generated for orphaned sections at link time.
Signed-off-by: Jan Van Winkel <jan.van_winkel@dxplore.eu>
Kinetis SoCs have a 16-byte flash configuration field that must be
loaded at a specific address in flash. This field is not needed if we
are building an image to be chainloaded by MCUboot or a RAM-only image,
so we can exlude it in these cases and recover some wasted flash.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The CC3235SF requires a debug header to be placed at the beginning of
internal flash, so that the bootloader does not automatically overwrite
the flash memory with the program saved in external flash.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Consistently place C++ use of extern "C" after all include directives,
within the negative branch of _ASMLANGUAGE if used.
In arch.h the extern "C" in the including context is left active during
include of target-specific mpu headers to avoid more complex
restructuring.
Background from issue #17997:
Declarations that use C linkage should be placed within extern "C"
so the language linkage is correct when the header is included by
a C++ compiler.
Similarly #include directives should be outside the extern "C" to
ensure the language-specific default linkage is applied to any
declarations provided by the included header.
See: https://en.cppreference.com/w/cpp/language/language_linkage
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Cortex R has a write buffer that can cause reordering problems when
accessing memory mapped registers. Use memory barries to make sure that
these accesses are performed in the desired order.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
These defines are specific to the Cortex-M. Move them to their own
header file to prepare for Cortex-R support.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
Because NXP MPU's regions are dynamically enabled/disabled, USB
device's access maybe restricted when switching out of a task.
Background DMA transfers to/from RAM may happen during MPU region
reconfiguration or core idling.
Enabled USB (Kinetis MPU Master 4) to always have access to RAM address
space.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
This is now called z_arch_esf_t, conforming to our naming
convention.
This needs to remain a typedef due to how our offset generation
header mechanism works.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We had a function that did this, but it was dead code.
Move to fatal.c and call from z_arm_fatal_error().
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
* z_NanoFatalErrorHandler() is now moved to common kernel code
and renamed z_fatal_error(). Arches dump arch-specific info
before calling.
* z_SysFatalErrorHandler() is now moved to common kernel code
and renamed k_sys_fatal_error_handler(). It is now much simpler;
the default policy is simply to lock interrupts and halt the system.
If an implementation of this function returns, then the currently
running thread is aborted.
* New arch-specific APIs introduced:
- z_arch_system_halt() simply powers off or halts the system.
* We now have a standard set of fatal exception reason codes,
namespaced under K_ERR_*
* CONFIG_SIMPLE_FATAL_ERROR_HANDLER deleted
* LOG_PANIC() calls moved to k_sys_fatal_error_handler()
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We are standardizing to a arch-independent set of exception
reason codes, don't overload it with internal state of
the ARM fault handling code.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit adds a DTCM (Device Tightly Coupled Memory) section for
Cortex F7 MCUs. The Address and length is defined in the corresponding
device tree file.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
When code relocation enabled, there will be serval regions holding
text. And then there will be function call between these .text
regions, when distance between caller and callee is too far, linker
will automatically generate and insert veneer functions. And these
veneer functions will be located right after the last instruction
in the .text region by the linker. So these code will be put in the
memory reserved for priv_stacks text and kobject text if they don't
consume all the reserved memory. Or the veneer functions will be put
before the reserved memory if there isn't code in the reserved
memory. And then in the user mode building process, there will be
different memory layout and it will cause usr mode not working.
And moving the memory reserved for priv_stacks text and kobject text
at the beginning of .text will avoid above problem. The detailed
analysis for this issue can be found on Github issue #17038.
Fixes: #17038.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Because NXP MPU's regions are dynamically enabled/disabled, ENET
device's access maybe restricted when switching out of a task.
Background DMA transfers from RAM to MAC/PHY may happen during MPU
region reconfiguration or core idling.
Enabled ENET (Kinetis MPU Master 3) to always have access to RAM address
space.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
move misc/util.h to sys/util.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We introduce a new define to describe the alignment for a
privilege stack buffer. This macro definition is used by the
privilege stack generation script, to determine the required
alignment of threads' privilege stacks when building with
support for user mode.
We cannot use Z_THREAD_MIN_STACK_ALIGN in this case, because
the privilege stacks do not need to respect the minimum MPU
region alignment requirement, unless, of course, this is
enforced via the MPU Stack Guard feature.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit re-organizes the macro definitions in arch.h for
the ARM architecture. In particular, the commit:
- defines the minimum alignment requirement for thread stacks,
that is, excluding alignment requirement for (possible)
MPU stack guards.
- defines convenience macros for the MPU stack guard align and
size for threads using the FP services under Shared registers
mode (CONFIG_FP_SHARING=y). For that, a hidden Kconfig option
is defined in arch/arm/core/cortex_m/mpu/Kconfig.
- enforces stack alignment with a wide MPU stack guard (128
bytes) under CONFIG_FP_SHARING=y for the ARMv7-M architecture,
which requires start address alignment with power-of-two and
region size.
The commit does not change the amount of stack that is reserved
with K_THREAD_STACK_DEFINE; it only determines the stack buffer
alignment as explained above.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
All architectures declare those variables the same way, no need to
define them per arch, instead put them in common. If someone deviates,
they can create their own header.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We had architectures doing this differently, some had a dedicated
sys_io.h file, some not. Unify how it is done by splitting the arch
specific sys_io implementation into a sys_io file and include it
instead.
Move bits_portable.h to arch/common and split the file so more
architecture can reuse some of the definitions here instead of
duplicating code.
Where applicable use the common sys_io/ffs definitions.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
It's useful to be able to inspect the key returned from
z_arch_irq_unlock() to see if interrupts were enabled at the point
where z_arch_irq_lock() was called. Architectures tend to represent
this is a simple way that doesn't require platform assembly to
inspect.
Adds a simple test to kernel/common that validates this predicate with
a nested lock.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
STM32WB HCI driver requires definition of 2 RAM regions to support
use of 3 shared memory sections: MAPPING_TABLE, MB_MEM1 and MB_MEM2.
In linker.ld, under conditions of HCI driver to be enabled,
define SRAM1 and SRAM2 based on input defined in stm32wb linker.
Then define the 3 sections MAPPING_TABLE, MB_MEM1 and MB_MEM
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
arm_core_mpu_dev.h is an internal API, and is not supposed to
be directly called by kernel / application functions, therefore,
we can move it inside arch/arm/core/cortex_m/mpu directory.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add ifdefs to handle the nrf91 case. This change will dynamically
place and size the NSC region according to nrf91 HW limitations.
Add Cmake check of NSC offset if manually set.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
Non-XIP system with FLASH_SIZE = 0 is no-flash system. And no-flash
system makes text, rodata, and data all in SRAM, so define the marco
ROM_ADDR to RAM_ADDR.
Fixes: #16027.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
on non-XIP system, SRAM is the default region, and relocated .data
section and .bss section of SRAM shouldn't be inserted between
_image_rom_start and _image_rom_end, because the memory region between
_image_rom_start and _image_rom_end will construct the mpu ro region.
Also for the newly added memory region on non-XIP system, the
relocated .text secition and .rodata section should also be mpu aligned.
Fixes: #16090.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Allows snippets to be placed in different locations:
- The noinit, rwdata and rodata output sections
- Two different locations for placing custom output sections,
one location for RAM and another for all other sections.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
The compiler was generating errors of the form
error: "CONFIG_ZERO_LATENCY_IRQS" is not defined, evaluates to 0
[-Werror=undef] when -Wundef is used and the config option was turned
off. Change check to ifdef.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
The ARM Cortex-M Exception Stack Frame (ESF) may consist of
several stack frame contexts (basic state context, additional
state context, FP context, etc.). To reflect these structural
properties, this commit re-factors the ESF, splitting out the
basic stack frame, holding the state context, into its own
struct container. The commit does not introduce behavioral
changes.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Under Unshared FP register mode we are not stacking the
FP context in exception entries, so we do not need to
include the FP registers bank in the exception stack
frame structure.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The size of the ROM region is now rounded up to the
nearest power of two; we no longer assume that RAM
is in a different part of memory.
Fixes: #15558
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
