Nicolas Pitre 7f74825958 riscv: add a qemu_riscv64 board ... This emulates a RISC-V in 64-bit mode on a SiFive FE310 dev board. Memory is tight so a few tests had to be disabled due to the extra memory usage compared to qemu_riscv32. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>		2019-08-09 09:11:45 -05:00
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can/frame
dfu
fs
jwt
logging	riscv: add a qemu_riscv64 board	2019-08-09 09:11:45 -05:00
settings	tests/subsys/settings/fcb: add check for target compatibility	2019-08-08 08:47:44 -05:00
shell/shell_history
storage/flash_map
usb