Nicolas Pitre 7f74825958 riscv: add a qemu_riscv64 board ... This emulates a RISC-V in 64-bit mode on a SiFive FE310 dev board. Memory is tight so a few tests had to be disabled due to the extra memory usage compared to qemu_riscv32. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>		2019-08-09 09:11:45 -05:00
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log_core	riscv: add a qemu_riscv64 board	2019-08-09 09:11:45 -05:00
log_list
log_msg	log_msg test: rework test_log_std_msg() to better cope with 64-bit builds	2019-06-24 08:58:52 +02:00
log_output	yaml: Remove redundant document separators	2019-06-19 10:40:10 +02:00