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zephyr/arch/x86/core
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Zide Chen d27f6cb5eb interrupt_controller: program local APIC LDR register for xAPIC 
If IO APIC is in logical destination mode, local APICs compare their
logical APIC ID defined in LDR (Logical Destination Register) with
the destination code sent with the interrupt to determine whether or not
to accept the incoming interrupt.

This patch programs LDR in xAPIC mode to support IO APIC logical mode.

The local APIC ID from local APIC ID register can't be used as the
'logical APIC ID' because LAPIC ID may not be consecutive numbers hence
it makes it impossible for LDR to encode 8 IDs within 8 bits.

This patch chooses 0 for BSP, and for APs, cpu_number which is the index
to x86_cpuboot[], which ultimately assigned in z_smp_init[].

Signed-off-by: Zide Chen <zide.chen@intel.com>
2020-05-08 22:32:39 -04:00
..
ia32 interrupt_controller: program local APIC LDR register for xAPIC 2020-05-08 22:32:39 -04:00
intel64 interrupt_controller: program local APIC LDR register for xAPIC 2020-05-08 22:32:39 -04:00
offsets kconfig: Rename x86 FPU sharing symbols 2020-05-08 10:58:33 +02:00
acpi.c
CMakeLists.txt
common.S
cpuhalt.c
early_serial.c x86: early_serial: extend to support MMIO UART 2020-05-07 10:11:35 +02:00
fatal.c kernel: add Z_STACK_PTR_ALIGN ARCH_STACK_PTR_ALIGN 2020-04-21 18:45:45 -04:00
ia32.cmake kconfig: Rename x86 FPU sharing symbols 2020-05-08 10:58:33 +02:00
intel64.cmake
Kconfig.ia32 kconfig: Rename x86 FPU sharing symbols 2020-05-08 10:58:33 +02:00
Kconfig.intel64
memmap.c x86: Rework rework x86 related code to use new DTS macros 2020-04-30 08:37:18 -05:00
multiboot.c
pcie.c
prep_c.c
reboot_rst_cnt.c
spec_ctrl.c
userspace.c kernel: add Z_STACK_PTR_ALIGN ARCH_STACK_PTR_ALIGN 2020-04-21 18:45:45 -04:00
x86_mmu.c x86: Rework rework x86 related code to use new DTS macros 2020-04-30 08:37:18 -05:00