Carlo Caione 6f36300219 drivers: timer: Add per-core ARM architected timer ... ARM cores may have a per-core architected timer, which provides per-cpu timers, attached to a GIC to deliver its per-processor interrupts via PPIs. This is the most common case supported by QEMU in the virt platform. This patch introduces support for this timer abstracting the way the timer registers are actually accessed. This is needed because different architectures (for example ARMv7-R vs ARMv8-A) use different registers and even the same architecture (ARMv8-A) can actually use different timers (ELx physical timers vs ELx virtual timers). So we introduce the common driver here but the actual SoC / architecture / board must provide the three helpers (arm_arch_timer_set_compare(), arm_arch_timer_toggle(), arm_arch_timer_count()) using an header file imported through the arch/cpu.h header file. Signed-off-by: Carlo Caione <ccaione@baylibre.com>		2020-02-01 08:08:43 -05:00
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arc
arm	dts: arm: stm32f4: add CAN_2 controller	2020-01-30 14:27:28 -05:00
bindings	drivers: timer: Add per-core ARM architected timer	2020-02-01 08:08:43 -05:00
common
nios2
posix
riscv	dts: riscv: rv32m1: add timer/pwm modules	2020-01-13 09:12:34 -06:00
x86	drivers/timer/hpet.c: migrate to devicetree	2019-09-17 22:37:09 +08:00
xtensa	intel_s1000: various fixes for build errors	2020-01-31 14:51:37 -05:00
binding-template.yaml	dts: edtlib: Add 'type: path' for path references	2020-01-08 08:02:00 -06:00
Kconfig