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82a6a467ec
zephyr/arch/riscv/core
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Daniel Leung 11e6b43090 tracing: roll thread switch in/out into thread stats functions 
Since the tracing of thread being switched in/out has the same
instrumentation points, we can roll the tracing function calls
into the one for thread stats gathering functions.
This avoids duplicating code to call another function.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-11-11 23:55:49 -05:00
..
offsets arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00
pmp arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00
CMakeLists.txt arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00
cpu_idle.c riscv: use standard MSTATUS 2020-01-06 13:27:45 -05:00
fatal.c arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00
irq_manage.c arch: Apply dynamic IRQ API change 2020-09-02 13:48:13 +02:00
irq_offload.c arch: Apply IRQ offload API change 2020-09-02 13:48:13 +02:00
isr.S tracing: roll thread switch in/out into thread stats functions 2020-11-11 23:55:49 -05:00
prep_c.c arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00
reset.S arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00
swap.S benchmarking: remove execution benchmarking code 2020-09-05 13:28:38 -05:00
thread.c arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00
tls.c riscv: add support for thread local storage 2020-10-24 10:52:00 -07:00
userspace.S arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00