mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-02 17:53:00 +00:00
ac74d8b652
Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
120 lines
3.3 KiB
C
120 lines
3.3 KiB
C
/* quark_se_clock_control.c - Clock controller driver for Quark SE */
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <misc/__assert.h>
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#include <board.h>
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#include <device.h>
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#include <init.h>
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#include <sys_io.h>
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#include <clock_control.h>
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#include <clock_control/quark_se_clock_control.h>
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_CLOCK_CONTROL_LEVEL
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#include <logging/sys_log.h>
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struct quark_se_clock_control_config {
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uint32_t base_address;
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};
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static inline int quark_se_clock_control_on(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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const struct quark_se_clock_control_config *info = dev->config->config_info;
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uint32_t subsys = POINTER_TO_INT(sub_system);
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if (sub_system == CLOCK_CONTROL_SUBSYS_ALL) {
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SYS_LOG_DBG("Enabling all clock gates on dev %p", dev);
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sys_write32(0xffffffff, info->base_address);
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return 0;
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}
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SYS_LOG_DBG("Enabling clock gate on dev %p subsystem %u", dev, subsys);
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return sys_test_and_set_bit(info->base_address, subsys);
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}
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static inline int quark_se_clock_control_off(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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const struct quark_se_clock_control_config *info = dev->config->config_info;
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uint32_t subsys = POINTER_TO_INT(sub_system);
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if (sub_system == CLOCK_CONTROL_SUBSYS_ALL) {
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SYS_LOG_DBG("Disabling all clock gates on dev %p", dev);
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sys_write32(0x00000000, info->base_address);
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return 0;
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}
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SYS_LOG_DBG("clock gate on dev %p subsystem %u", dev, subsys);
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return sys_test_and_clear_bit(info->base_address, subsys);
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}
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static const struct clock_control_driver_api quark_se_clock_control_api = {
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.on = quark_se_clock_control_on,
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.off = quark_se_clock_control_off,
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.get_rate = NULL,
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};
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int quark_se_clock_control_init(struct device *dev)
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{
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SYS_LOG_DBG("Quark Se clock controller driver initialized on device: "
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"%p", dev);
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return 0;
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}
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#ifdef CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL
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static struct quark_se_clock_control_config clock_quark_se_peripheral_config = {
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.base_address = CLOCK_PERIPHERAL_BASE_ADDR
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};
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DEVICE_AND_API_INIT(clock_quark_se_peripheral,
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CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME,
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&quark_se_clock_control_init,
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NULL, &clock_quark_se_peripheral_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&quark_se_clock_control_api);
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#endif /* CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL */
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#ifdef CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL
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static struct quark_se_clock_control_config clock_quark_se_external_config = {
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.base_address = CLOCK_EXTERNAL_BASE_ADDR
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};
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DEVICE_AND_API_INIT(clock_quark_se_external,
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CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL_DRV_NAME,
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&quark_se_clock_control_init,
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NULL, &clock_quark_se_external_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&quark_se_clock_control_api);
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#endif /* CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL */
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#ifdef CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR
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static struct quark_se_clock_control_config clock_quark_se_sensor_config = {
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.base_address = CLOCK_SENSOR_BASE_ADDR
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};
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DEVICE_AND_API_INIT(clock_quark_se_sensor,
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CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME,
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&quark_se_clock_control_init,
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NULL, &clock_quark_se_sensor_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&quark_se_clock_control_api);
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#endif /* CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR */
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