Kumar Gala a918d301fe drivers: adc: adc_sam0: rework devicetree support ... Rework the devicetree to utilize new DT_INST macros and extract per instance data for clocks from devicetree. We add a property ('calib-offset') for the SAM{D,E}5x family of SoCs that is the bit position offset from ADC0 BIASCOMP in the NVM Software Calibration Area Mapping. For ADC0 this is typically 0 and for ADC1 this will be 14. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>		2020-04-29 08:02:36 -05:00
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adc-controller.yaml
atmel,sam-afec.yaml	drivers: adc: adc_sam_afec: rework device tree support	2020-04-23 06:11:26 -05:00
atmel,sam0-adc.yaml	drivers: adc: adc_sam0: rework devicetree support	2020-04-29 08:02:36 -05:00
microchip,mcp320x-base.yaml	dts: bindings: add bindings for Microchip MCP320x	2020-03-27 16:17:06 +01:00
microchip,mcp3204.yaml	dts: bindings: add bindings for Microchip MCP320x	2020-03-27 16:17:06 +01:00
microchip,mcp3208.yaml	dts: bindings: add bindings for Microchip MCP320x	2020-03-27 16:17:06 +01:00
microchip,xec-adc.yaml
nordic,nrf-adc.yaml
nordic,nrf-saadc.yaml
nxp,kinetis-adc12.yaml
nxp,kinetis-adc16.yaml
st,stm32-adc.yaml
ti,lmp90xxx-base.yaml
ti,lmp90xxx-current.yaml
ti,lmp90077.yaml
ti,lmp90078.yaml
ti,lmp90079.yaml
ti,lmp90080.yaml
ti,lmp90097.yaml
ti,lmp90098.yaml
ti,lmp90099.yaml
ti,lmp90100.yaml