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https://github.com/zephyrproject-rtos/zephyr
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a918d301fe
Rework the devicetree to utilize new DT_INST macros and extract per
instance data for clocks from devicetree.
We add a property ('calib-offset') for the SAM{D,E}5x family of SoCs
that is the bit position offset from ADC0 BIASCOMP in the NVM Software
Calibration Area Mapping. For ADC0 this is typically 0 and for ADC1
this will be 14.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
49 lines
975 B
YAML
49 lines
975 B
YAML
# Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
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# SPDX-License-Identifier: Apache-2.0
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description: Atmel SAM0 family ADC
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compatible: "atmel,sam0-adc"
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include: adc-controller.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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clocks:
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required: true
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clock-names:
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required: true
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gclk:
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type: int
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required: true
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description: generic clock generator source
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prescaler:
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type: int
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required: true
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description: clock prescaler divisor applied to the generic clock
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"#io-channel-cells":
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const: 1
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calib-offset:
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type: int
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required: false
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description: |
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bit position offset in NVM SW Calib for start of ADC0 BIASCOMP field.
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This property is expected to be set on SAM{D,E}5x family of SoCs.
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For ADC0 this should be 0, and for ADC1 this should be 14.
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enum:
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- 0
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- 14
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io-channel-cells:
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- input
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