mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-31 17:25:21 +00:00
6e27478c3d
This code had one purpose only, feed timing information into a test and was not used by anything else. The custom trace points unfortunatly were not accurate and this test was delivering informatin that conflicted with other tests we have due to placement of such trace points in the architecture and kernel code. For such measurements we are planning to use the tracing functionality in a special mode that would be used for metrics without polluting the architecture and kernel code with additional tracing and timing code. Furthermore, much of the assembly code used had issues. Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Daniel Leung <daniel.leung@intel.com>
507 lines
15 KiB
ArmAsm
507 lines
15 KiB
ArmAsm
/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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* Copyright (c) 2018 Foundries.io Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <offsets_short.h>
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#include <arch/cpu.h>
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#include <sys/util.h>
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#include <kernel.h>
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/* Convenience macros for loading/storing register states. */
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#define DO_FP_CALLER_SAVED(op, reg) \
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op ft0, __z_arch_esf_t_ft0_OFFSET(reg) ;\
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op ft1, __z_arch_esf_t_ft1_OFFSET(reg) ;\
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op ft2, __z_arch_esf_t_ft2_OFFSET(reg) ;\
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op ft3, __z_arch_esf_t_ft3_OFFSET(reg) ;\
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op ft4, __z_arch_esf_t_ft4_OFFSET(reg) ;\
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op ft5, __z_arch_esf_t_ft5_OFFSET(reg) ;\
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op ft6, __z_arch_esf_t_ft6_OFFSET(reg) ;\
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op ft7, __z_arch_esf_t_ft7_OFFSET(reg) ;\
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op ft8, __z_arch_esf_t_ft8_OFFSET(reg) ;\
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op ft9, __z_arch_esf_t_ft9_OFFSET(reg) ;\
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op ft10, __z_arch_esf_t_ft10_OFFSET(reg) ;\
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op ft11, __z_arch_esf_t_ft11_OFFSET(reg) ;\
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op fa0, __z_arch_esf_t_fa0_OFFSET(reg) ;\
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op fa1, __z_arch_esf_t_fa1_OFFSET(reg) ;\
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op fa2, __z_arch_esf_t_fa2_OFFSET(reg) ;\
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op fa3, __z_arch_esf_t_fa3_OFFSET(reg) ;\
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op fa4, __z_arch_esf_t_fa4_OFFSET(reg) ;\
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op fa5, __z_arch_esf_t_fa5_OFFSET(reg) ;\
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op fa6, __z_arch_esf_t_fa6_OFFSET(reg) ;\
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op fa7, __z_arch_esf_t_fa7_OFFSET(reg) ;
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#define STORE_FP_CALLER_SAVED(reg) \
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DO_FP_CALLER_SAVED(RV_OP_STOREFPREG, reg)
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#define LOAD_FP_CALLER_SAVED(reg) \
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DO_FP_CALLER_SAVED(RV_OP_LOADFPREG, reg)
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#define DO_FP_CALLEE_SAVED(op, reg) \
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op fs0, _thread_offset_to_fs0(reg) ;\
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op fs1, _thread_offset_to_fs1(reg) ;\
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op fs2, _thread_offset_to_fs2(reg) ;\
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op fs3, _thread_offset_to_fs3(reg) ;\
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op fs4, _thread_offset_to_fs4(reg) ;\
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op fs5, _thread_offset_to_fs5(reg) ;\
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op fs6, _thread_offset_to_fs6(reg) ;\
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op fs7, _thread_offset_to_fs7(reg) ;\
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op fs8, _thread_offset_to_fs8(reg) ;\
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op fs9, _thread_offset_to_fs9(reg) ;\
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op fs10, _thread_offset_to_fs10(reg) ;\
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op fs11, _thread_offset_to_fs11(reg) ;
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#define STORE_FP_CALLEE_SAVED(reg) \
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frcsr t2 ;\
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RV_OP_STOREREG t2, _thread_offset_to_fcsr(reg) ;\
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DO_FP_CALLEE_SAVED(RV_OP_STOREFPREG, reg)
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#define LOAD_FP_CALLEE_SAVED(reg) \
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RV_OP_LOADREG t2, _thread_offset_to_fcsr(reg) ;\
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fscsr x0, t2 ;\
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DO_FP_CALLEE_SAVED(RV_OP_LOADFPREG, reg)
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/* imports */
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GDATA(_sw_isr_table)
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GTEXT(__soc_is_irq)
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GTEXT(__soc_handle_irq)
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GTEXT(_Fault)
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#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
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GTEXT(__soc_save_context)
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GTEXT(__soc_restore_context)
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#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
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GTEXT(_k_neg_eagain)
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GTEXT(_is_next_thread_current)
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GTEXT(z_get_next_ready_thread)
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#ifdef CONFIG_TRACING
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GTEXT(sys_trace_thread_switched_in)
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GTEXT(sys_trace_isr_enter)
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#endif
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#ifdef CONFIG_IRQ_OFFLOAD
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GTEXT(_offload_routine)
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#endif
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/* exports */
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GTEXT(__irq_wrapper)
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/* use ABI name of registers for the sake of simplicity */
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/*
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* Generic architecture-level IRQ handling, along with callouts to
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* SoC-specific routines.
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*
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* Architecture level IRQ handling includes basic context save/restore
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* of standard registers and calling ISRs registered at Zephyr's driver
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* level.
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*
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* Since RISC-V does not completely prescribe IRQ handling behavior,
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* implementations vary (some implementations also deviate from
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* what standard behavior is defined). Hence, the arch level code expects
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* the following functions to be provided at the SOC level:
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*
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* - __soc_is_irq: decide if we're handling an interrupt or an exception
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* - __soc_handle_irq: handle SoC-specific details for a pending IRQ
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* (e.g. clear a pending bit in a SoC-specific register)
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*
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* If CONFIG_RISCV_SOC_CONTEXT_SAVE=y, calls to SoC-level context save/restore
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* routines are also made here. For details, see the Kconfig help text.
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*/
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/*
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* Handler called upon each exception/interrupt/fault
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* In this architecture, system call (ECALL) is used to perform context
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* switching or IRQ offloading (when enabled).
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*/
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SECTION_FUNC(exception.entry, __irq_wrapper)
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/* Allocate space on thread stack to save registers */
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addi sp, sp, -__z_arch_esf_t_SIZEOF
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/* Save caller-saved registers on current thread stack. */
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RV_OP_STOREREG ra, __z_arch_esf_t_ra_OFFSET(sp)
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RV_OP_STOREREG gp, __z_arch_esf_t_gp_OFFSET(sp)
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RV_OP_STOREREG tp, __z_arch_esf_t_tp_OFFSET(sp)
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RV_OP_STOREREG t0, __z_arch_esf_t_t0_OFFSET(sp)
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RV_OP_STOREREG t1, __z_arch_esf_t_t1_OFFSET(sp)
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RV_OP_STOREREG t2, __z_arch_esf_t_t2_OFFSET(sp)
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RV_OP_STOREREG t3, __z_arch_esf_t_t3_OFFSET(sp)
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RV_OP_STOREREG t4, __z_arch_esf_t_t4_OFFSET(sp)
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RV_OP_STOREREG t5, __z_arch_esf_t_t5_OFFSET(sp)
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RV_OP_STOREREG t6, __z_arch_esf_t_t6_OFFSET(sp)
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RV_OP_STOREREG a0, __z_arch_esf_t_a0_OFFSET(sp)
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RV_OP_STOREREG a1, __z_arch_esf_t_a1_OFFSET(sp)
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RV_OP_STOREREG a2, __z_arch_esf_t_a2_OFFSET(sp)
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RV_OP_STOREREG a3, __z_arch_esf_t_a3_OFFSET(sp)
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RV_OP_STOREREG a4, __z_arch_esf_t_a4_OFFSET(sp)
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RV_OP_STOREREG a5, __z_arch_esf_t_a5_OFFSET(sp)
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RV_OP_STOREREG a6, __z_arch_esf_t_a6_OFFSET(sp)
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RV_OP_STOREREG a7, __z_arch_esf_t_a7_OFFSET(sp)
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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/* Assess whether floating-point registers need to be saved. */
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la t0, _kernel
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RV_OP_LOADREG t0, _kernel_offset_to_current(t0)
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RV_OP_LOADREG t0, _thread_offset_to_user_options(t0)
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andi t0, t0, K_FP_REGS
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RV_OP_STOREREG t0, __z_arch_esf_t_fp_state_OFFSET(sp)
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beqz t0, skip_store_fp_caller_saved
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STORE_FP_CALLER_SAVED(sp)
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skip_store_fp_caller_saved:
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#endif
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/* Save MEPC register */
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csrr t0, mepc
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RV_OP_STOREREG t0, __z_arch_esf_t_mepc_OFFSET(sp)
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/* Save SOC-specific MSTATUS register */
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csrr t0, mstatus
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RV_OP_STOREREG t0, __z_arch_esf_t_mstatus_OFFSET(sp)
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#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
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/* Handle context saving at SOC level. */
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addi a0, sp, __z_arch_esf_t_soc_context_OFFSET
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jal ra, __soc_save_context
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#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
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/*
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* Check if exception is the result of an interrupt or not.
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* (SOC dependent). Following the RISC-V architecture spec, the MSB
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* of the mcause register is used to indicate whether an exception
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* is the result of an interrupt or an exception/fault. But for some
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* SOCs (like pulpino or riscv-qemu), the MSB is never set to indicate
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* interrupt. Hence, check for interrupt/exception via the __soc_is_irq
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* function (that needs to be implemented by each SOC). The result is
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* returned via register a0 (1: interrupt, 0 exception)
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*/
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jal ra, __soc_is_irq
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/* If a0 != 0, jump to is_interrupt */
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addi t1, x0, 0
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bnez a0, is_interrupt
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/*
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* If the exception is the result of an ECALL, check whether to
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* perform a context-switch or an IRQ offload. Otherwise call _Fault
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* to report the exception.
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*/
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csrr t0, mcause
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li t2, SOC_MCAUSE_EXP_MASK
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and t0, t0, t2
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li t1, SOC_MCAUSE_ECALL_EXP
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/*
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* If mcause == SOC_MCAUSE_ECALL_EXP, handle system call,
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* otherwise handle fault
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*/
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beq t0, t1, is_syscall
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/*
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* Call _Fault to handle exception.
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* Stack pointer is pointing to a z_arch_esf_t structure, pass it
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* to _Fault (via register a0).
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* If _Fault shall return, set return address to no_reschedule
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* to restore stack.
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*/
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addi a0, sp, 0
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la ra, no_reschedule
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tail _Fault
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is_syscall:
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/*
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* A syscall is the result of an ecall instruction, in which case the
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* MEPC will contain the address of the ecall instruction.
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* Increment saved MEPC by 4 to prevent triggering the same ecall
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* again upon exiting the ISR.
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*
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* It's safe to always increment by 4, even with compressed
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* instructions, because the ecall instruction is always 4 bytes.
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*/
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RV_OP_LOADREG t0, __z_arch_esf_t_mepc_OFFSET(sp)
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addi t0, t0, 4
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RV_OP_STOREREG t0, __z_arch_esf_t_mepc_OFFSET(sp)
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#ifdef CONFIG_IRQ_OFFLOAD
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/*
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* Determine if the system call is the result of an IRQ offloading.
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* Done by checking if _offload_routine is not pointing to NULL.
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* If NULL, jump to reschedule to perform a context-switch, otherwise,
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* jump to is_interrupt to handle the IRQ offload.
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*/
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la t0, _offload_routine
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RV_OP_LOADREG t1, 0x00(t0)
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bnez t1, is_interrupt
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#endif
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/*
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* Go to reschedule to handle context-switch
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*/
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j reschedule
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is_interrupt:
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/*
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* Save current thread stack pointer and switch
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* stack pointer to interrupt stack.
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*/
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/* Save thread stack pointer to temp register t0 */
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addi t0, sp, 0
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/* Switch to interrupt stack */
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la t2, _kernel
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RV_OP_LOADREG sp, _kernel_offset_to_irq_stack(t2)
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/*
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* Save thread stack pointer on interrupt stack
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* In RISC-V, stack pointer needs to be 16-byte aligned
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*/
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addi sp, sp, -16
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RV_OP_STOREREG t0, 0x00(sp)
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on_irq_stack:
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/* Increment _kernel.cpus[0].nested variable */
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lw t3, _kernel_offset_to_nested(t2)
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addi t3, t3, 1
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sw t3, _kernel_offset_to_nested(t2)
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#ifdef CONFIG_IRQ_OFFLOAD
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/*
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* If we are here due to a system call, t1 register should != 0.
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* In this case, perform IRQ offloading, otherwise jump to call_irq
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*/
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beqz t1, call_irq
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/*
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* Call z_irq_do_offload to handle IRQ offloading.
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* Set return address to on_thread_stack in order to jump there
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* upon returning from z_irq_do_offload
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*/
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la ra, on_thread_stack
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tail z_irq_do_offload
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call_irq:
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#endif /* CONFIG_IRQ_OFFLOAD */
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#ifdef CONFIG_TRACING_ISR
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call sys_trace_isr_enter
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#endif
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/* Get IRQ causing interrupt */
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csrr a0, mcause
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li t0, SOC_MCAUSE_EXP_MASK
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and a0, a0, t0
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/*
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* Clear pending IRQ generating the interrupt at SOC level
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* Pass IRQ number to __soc_handle_irq via register a0
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*/
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jal ra, __soc_handle_irq
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/*
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* Call corresponding registered function in _sw_isr_table.
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* (table is 2-word wide, we should shift index accordingly)
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*/
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la t0, _sw_isr_table
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slli a0, a0, (RV_REGSHIFT + 1)
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add t0, t0, a0
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/* Load argument in a0 register */
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RV_OP_LOADREG a0, 0x00(t0)
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/* Load ISR function address in register t1 */
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RV_OP_LOADREG t1, RV_REGSIZE(t0)
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/* Call ISR function */
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jalr ra, t1
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on_thread_stack:
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/* Get reference to _kernel */
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la t1, _kernel
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/* Decrement _kernel.cpus[0].nested variable */
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lw t2, _kernel_offset_to_nested(t1)
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addi t2, t2, -1
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sw t2, _kernel_offset_to_nested(t1)
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/* Restore thread stack pointer */
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RV_OP_LOADREG t0, 0x00(sp)
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addi sp, t0, 0
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#ifdef CONFIG_STACK_SENTINEL
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call z_check_stack_sentinel
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la t1, _kernel
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#endif
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#ifdef CONFIG_PREEMPT_ENABLED
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/*
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* Check if we need to perform a reschedule
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*/
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/* Get pointer to _kernel.current */
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RV_OP_LOADREG t2, _kernel_offset_to_current(t1)
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/*
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* Check if next thread to schedule is current thread.
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* If yes do not perform a reschedule
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*/
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RV_OP_LOADREG t3, _kernel_offset_to_ready_q_cache(t1)
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beq t3, t2, no_reschedule
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#else
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j no_reschedule
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#endif /* CONFIG_PREEMPT_ENABLED */
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reschedule:
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#if CONFIG_TRACING
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call sys_trace_thread_switched_out
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#endif
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/* Get reference to _kernel */
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la t0, _kernel
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/* Get pointer to _kernel.current */
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RV_OP_LOADREG t1, _kernel_offset_to_current(t0)
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/*
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* Save callee-saved registers of current thread
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* prior to handle context-switching
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*/
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RV_OP_STOREREG s0, _thread_offset_to_s0(t1)
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RV_OP_STOREREG s1, _thread_offset_to_s1(t1)
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RV_OP_STOREREG s2, _thread_offset_to_s2(t1)
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RV_OP_STOREREG s3, _thread_offset_to_s3(t1)
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RV_OP_STOREREG s4, _thread_offset_to_s4(t1)
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RV_OP_STOREREG s5, _thread_offset_to_s5(t1)
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RV_OP_STOREREG s6, _thread_offset_to_s6(t1)
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RV_OP_STOREREG s7, _thread_offset_to_s7(t1)
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RV_OP_STOREREG s8, _thread_offset_to_s8(t1)
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RV_OP_STOREREG s9, _thread_offset_to_s9(t1)
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RV_OP_STOREREG s10, _thread_offset_to_s10(t1)
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RV_OP_STOREREG s11, _thread_offset_to_s11(t1)
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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/* Assess whether floating-point registers need to be saved. */
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RV_OP_LOADREG t2, _thread_offset_to_user_options(t1)
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andi t2, t2, K_FP_REGS
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beqz t2, skip_store_fp_callee_saved
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STORE_FP_CALLEE_SAVED(t1)
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skip_store_fp_callee_saved:
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#endif
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/*
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* Save stack pointer of current thread and set the default return value
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* of z_swap to _k_neg_eagain for the thread.
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*/
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RV_OP_STOREREG sp, _thread_offset_to_sp(t1)
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la t2, _k_neg_eagain
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lw t3, 0x00(t2)
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sw t3, _thread_offset_to_swap_return_value(t1)
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/* Get next thread to schedule. */
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RV_OP_LOADREG t1, _kernel_offset_to_ready_q_cache(t0)
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/*
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* Set _kernel.current to new thread loaded in t1
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*/
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RV_OP_STOREREG t1, _kernel_offset_to_current(t0)
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/* Switch to new thread stack */
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RV_OP_LOADREG sp, _thread_offset_to_sp(t1)
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/* Restore callee-saved registers of new thread */
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RV_OP_LOADREG s0, _thread_offset_to_s0(t1)
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RV_OP_LOADREG s1, _thread_offset_to_s1(t1)
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RV_OP_LOADREG s2, _thread_offset_to_s2(t1)
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RV_OP_LOADREG s3, _thread_offset_to_s3(t1)
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RV_OP_LOADREG s4, _thread_offset_to_s4(t1)
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RV_OP_LOADREG s5, _thread_offset_to_s5(t1)
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RV_OP_LOADREG s6, _thread_offset_to_s6(t1)
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RV_OP_LOADREG s7, _thread_offset_to_s7(t1)
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RV_OP_LOADREG s8, _thread_offset_to_s8(t1)
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RV_OP_LOADREG s9, _thread_offset_to_s9(t1)
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RV_OP_LOADREG s10, _thread_offset_to_s10(t1)
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RV_OP_LOADREG s11, _thread_offset_to_s11(t1)
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|
|
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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/* Determine if we need to restore floating-point registers. */
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RV_OP_LOADREG t2, _thread_offset_to_user_options(t1)
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andi t2, t2, K_FP_REGS
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beqz t2, skip_load_fp_callee_saved
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|
|
|
/*
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|
* If we are switching from a thread with floating-point disabled the
|
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* mstatus FS bits will still be cleared, which can cause an illegal
|
|
* instruction fault. Set the FS state before restoring the registers.
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|
* mstatus will be restored later on.
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*/
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|
li t2, MSTATUS_FS_INIT
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|
csrrs x0, mstatus, t2
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|
|
|
LOAD_FP_CALLEE_SAVED(t1)
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|
|
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skip_load_fp_callee_saved:
|
|
#endif
|
|
|
|
#if CONFIG_TRACING
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|
call sys_trace_thread_switched_in
|
|
#endif
|
|
|
|
no_reschedule:
|
|
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
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|
/* Restore context at SOC level */
|
|
addi a0, sp, __z_arch_esf_t_soc_context_OFFSET
|
|
jal ra, __soc_restore_context
|
|
#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
|
|
|
|
/* Restore MEPC register */
|
|
RV_OP_LOADREG t0, __z_arch_esf_t_mepc_OFFSET(sp)
|
|
csrw mepc, t0
|
|
|
|
/* Restore SOC-specific MSTATUS register */
|
|
RV_OP_LOADREG t0, __z_arch_esf_t_mstatus_OFFSET(sp)
|
|
csrw mstatus, t0
|
|
|
|
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
|
|
/*
|
|
* Determine if we need to restore floating-point registers. This needs
|
|
* to happen before restoring integer registers to avoid stomping on
|
|
* t0.
|
|
*/
|
|
RV_OP_LOADREG t0, __z_arch_esf_t_fp_state_OFFSET(sp)
|
|
beqz t0, skip_load_fp_caller_saved
|
|
LOAD_FP_CALLER_SAVED(sp)
|
|
|
|
skip_load_fp_caller_saved:
|
|
#endif
|
|
|
|
/* Restore caller-saved registers from thread stack */
|
|
RV_OP_LOADREG ra, __z_arch_esf_t_ra_OFFSET(sp)
|
|
RV_OP_LOADREG gp, __z_arch_esf_t_gp_OFFSET(sp)
|
|
RV_OP_LOADREG tp, __z_arch_esf_t_tp_OFFSET(sp)
|
|
RV_OP_LOADREG t0, __z_arch_esf_t_t0_OFFSET(sp)
|
|
RV_OP_LOADREG t1, __z_arch_esf_t_t1_OFFSET(sp)
|
|
RV_OP_LOADREG t2, __z_arch_esf_t_t2_OFFSET(sp)
|
|
RV_OP_LOADREG t3, __z_arch_esf_t_t3_OFFSET(sp)
|
|
RV_OP_LOADREG t4, __z_arch_esf_t_t4_OFFSET(sp)
|
|
RV_OP_LOADREG t5, __z_arch_esf_t_t5_OFFSET(sp)
|
|
RV_OP_LOADREG t6, __z_arch_esf_t_t6_OFFSET(sp)
|
|
RV_OP_LOADREG a0, __z_arch_esf_t_a0_OFFSET(sp)
|
|
RV_OP_LOADREG a1, __z_arch_esf_t_a1_OFFSET(sp)
|
|
RV_OP_LOADREG a2, __z_arch_esf_t_a2_OFFSET(sp)
|
|
RV_OP_LOADREG a3, __z_arch_esf_t_a3_OFFSET(sp)
|
|
RV_OP_LOADREG a4, __z_arch_esf_t_a4_OFFSET(sp)
|
|
RV_OP_LOADREG a5, __z_arch_esf_t_a5_OFFSET(sp)
|
|
RV_OP_LOADREG a6, __z_arch_esf_t_a6_OFFSET(sp)
|
|
RV_OP_LOADREG a7, __z_arch_esf_t_a7_OFFSET(sp)
|
|
|
|
/* Release stack space */
|
|
addi sp, sp, __z_arch_esf_t_SIZEOF
|
|
|
|
/* Call SOC_ERET to exit ISR */
|
|
SOC_ERET
|