mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-09 03:55:59 +00:00
e3f2fa4f89
This interrupt controller is a designware IP that combines several sources of interrupt into one line that is then routed to the parent controller. This implementation supports only the regular irqs with no support for priority filtering and vectored interrupts. Firqs are also not supported. Change-Id: I8bdf6f8df4632b6d7e8a3ba9a77116771d034a48 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
12 lines
736 B
CMake
12 lines
736 B
CMake
zephyr_sources_ifdef(CONFIG_ARCV2_INTERRUPT_UNIT arcv2_irq_unit.c)
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zephyr_sources_ifdef(CONFIG_IOAPIC ioapic_intr.c)
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zephyr_sources_ifdef(CONFIG_LOAPIC loapic_intr.c system_apic.c)
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zephyr_sources_ifdef(CONFIG_LOAPIC_SPURIOUS_VECTOR loapic_spurious.c)
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zephyr_sources_ifdef(CONFIG_MVIC mvic.c)
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zephyr_sources_ifdef(CONFIG_PIC_DISABLE i8259.c)
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zephyr_sources_ifdef(CONFIG_PLIC_FE310 plic_fe310.c)
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zephyr_sources_ifdef(CONFIG_SHARED_IRQ shared_irq.c)
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zephyr_sources_ifdef(CONFIG_SOC_FAMILY_STM32 exti_stm32.c)
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zephyr_sources_ifdef(CONFIG_CAVS_ICTL cavs_ictl.c)
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zephyr_sources_ifdef(CONFIG_DW_ICTL dw_ictl.c)
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