This commit adds a node for the ASMedia 2364 controller that acts as an
I2C master on the I2C0 bus. This node contains the GPIO used by the MCU
to notify the ASM2364 that data are available to read.
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
This patch adds a DTS binding for the Texas Instruments LP5030 and
LP5036 I2C LED controllers. They are respectively providing up to 30
and 36 channels (i.e. 10 or 12 RGB LEDs).
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
The led-controller DT binding gathers some common properties for LED
controllers and for the LED child nodes.
One notable property is "color-mapping" which allows to define a channel
to color mapping for multicolor LEDs.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
By default the I2C timing (I2C_TIMINGR register) of I2C V2 peripheral is
computed depending on clocks at runtime with relatively low precision.
This optional property allows to provide a list of pre-computed values
(typically computed from STM32CubeMX SW tool) instead of using runtime
algorithm.
The precomputed value is only valid for a given clock configuration and
I2C speed setting, so this valid configuration is provided with each
value entry.
Signed-off-by: Laurent Meunier <laurent.meunier@st.com>
The spi_flash_w25qxxdv driver has been superseded by the generic
spi_nor driver for over a year. The only non-refactoring change to
the W25Q driver in the last 18 months was done to support a backport
to 1.14.
All devices supported by spi_flash_w25qxxdv driver are expected to be
supported by the spi_nor driver, using the standard `jedec,spi-nor`
devicetree compatible. No in-tree devicetree files make use of this
driver.
Remove the confusion about which driver to select by removing the
unmaintained redundant driver.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
In the SoC that comes on the nRF5340 DK the number of MPU
regions in the nRF5340 Network MCU is 8, instead of 16. We
fix this in DTS by introducing different .dtsi headers for the
different SoC part variants: the nrf340 Engineering A (first
SoC revision, present in the nRF5340 PDK) and the nrf5340
(second SoC revision, present on nRF5340 DK).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
As a general rule devicetree properties should correspond to hardware
description or configuration. In cases where a Zephyr driver receives
instance-specific configuration data from a devicetree property that
property should be marked as being Zephyr-specific. Rename
concat-buf-size to zephyr,concat-buf-size to follow this guideline.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The Nordic TWIM peripheral generates a start condition for each bus
transaction. Devices such as the SSD1306 display and some NXP sensors
can only tolerate the presence of a start condition and device address
after a stop condition. Those devices will not operate correctly when
these signals are observed while the bus is already active. This
motivated the addition of a RAM buffer into which message fragments
could be collected so TWIM can transmit them without injecting
unnecessary start conditions.
However many I2C devices interpret these signals as a repeated start
and ignore them and so function properly without a buffer
concatenating the message fragments.
There is no default for the concat-buf-size property, and the previous
strict requirement for one when performing scatter/gather I/O
transactions broke working drivers for devices that tolerate the
repeated starts. Allow those drivers to work by respecting the
property description and attempting to concatenate messages only if a
buffer in which to place them has been provided.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Added support for hardware flow control in EFM32 UART driver.
Signed-off-by: Timo Dammes <timo.dammes@lemonbeat.com>
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Use the new SFDP infrastructure to read the supported erase type sizes
and commands from the Basic Flash Parameters block. This removes the
need for explicit reference to most block sizes from this driver.
We're also seeing devices where the page size is not 256 bytes.
Accommodate them.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
With SFDP support we no longer need to get the JEDEC ID or device size
from devicetree. Make them optional in drivers that have been
converted to support SFDP. When runtime SFDP is not enabled the
presence of the required properties will be verified at build-time.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Allow the devicetree binding for a jedec,spi-nor device to provide the
device capabilities by encoding the Serial Flash Discoverable
Parameters Basic Flash Parameters table in the devicetree node. This
supports applications where a specific flash device will be used and
runtime discovery of device capabilities is not desired.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Add IUART driver based on MCUX SDK. This driver is used to provide
serial console support on i.MX8M Mini SoC.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Add devicetree bindings for the Xilinx AXI GPIO v2 IP. This GPIO
controller has an optional "GPIO2" port, which is not always present.
The Xilinx specific devicetree property names and their meaning match a
subset of what can automatically be generated based on the FPGA logic
design using https://github.com/Xilinx/device-tree-xlnx. These
properties are also used by the Linux kernel.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Change the documentation for the arm,dtcm (Data Tightly Coupled Memory)
to reflect that it is not specific to the Cortex-M7 (but also present
on e.g. the Cortex-M1).
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Skeleton board support for the npcx7m6fb evaluation board from Nuvoton
Technology. This CL also includes:
1. Add ecst python scripts to append the header used by NPCX ROM.
2. Add openocd configuration scripts for "west flash".
3. Add monitor FW binary file for programing/verifying embedded flash
in NPCX series.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Add pin controller support for Nuvoton NPCX series
Add pin-mux controller support for Nuvoton NPCX series.
This CL includes:
1. Add pin controller device tree declarations and introduce alt-cells
to select pads' functionality.
2. Add npcx7-alts-map.dtsi since the mapping between IO and controller
is irregular and vary in each chip series.
3. Add nuvoton,npcx-pinctrl-def.yaml and its declarations to change all
pads' functionality to GPIO by default.
4. Pinmux controller driver implementation.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Add clock controller support for Nuvoton NPCX series. This CL includes:
1. Add clock controller device tree declarations.
2. Introduce clock-cells in yaml file clock tree to get module's source
clock and turn off/on the its clock
3. Clock controller driver implementation.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Initial support for Nuvoton NPCX7M6FB SoC of NPCX series which is a chip
family of embedded controllers (EC) and targeted for a wide range of
portable applications. We implemented the SoC skeleton in
soc/arm/nuvoton_npcx since there're many chip families in Nuvoton and
aim to different markets such as PC, General MCU, and Audio. The
architectures and hardware modules are different between them. Hence, we
suggest using the company name plus with chip series for better
understanding.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The FT5336 driver has been improved and generalized so that multiple
Focaltech touch controllers can be supported using the same single
driver. According to specifications the following list of controller
variants should be supported: FT5x06, FT5606, FT5x16, FT6x06, Ft6x36,
FT5x06i, FT5336, FT3316, FT5436i, FT5336i and FT5x46.
Tested using ER-TFTM028-4 display module (FT6X06).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The EFR32MG21 uses a different kind of clock for watchdogs.
It requires an additional peripheral-id parameter in the dts to get the
proper clock as it is based on the watchdog's ID i.e., cmuClock_WDOG#.
Signed-off-by: Steven Lemaire <steven.lemaire@zii.aero>
The peripheral is the same on the SAMD20 and SAMD21 except for
different clock and interrupt settings. There is no DAC on the SAMR21.
Leave disabled by default as the DAC is fairly power hungry.
Signed-off-by: Michael Hope <mlhx@google.com>
This commit enables support for parsing 'fixed-link' node when it
is added to node described in 'ethernet,fixed-link.yaml'.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This patch adds description for 'fixed-link' node in ethernet DTS
node. It supports setting speed and duplex.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit adds the device tree nodes and bindings for the I2C
controllers of the LPC11U6X MCUs
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
This commit adds basic support for the clock controller used in
lpc11u6x MCUs.
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
This commit adds a bindings for the clock controller used in lpc11u6x
MCUs. It also adds a clock-controller node for the lpc11u6x soc series.
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
This patch adds the DT nodes and binding for the pinmux registers,
aka IOCON (I/O control), found on the LPC11U6x MCUs.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Now that the patches have landed, enable more of the peripherals on
the board.
In particular:
* Enable PWM on the LED
* Enable the SPI, USB, and DMA
* Enable the bootloader support
* Add to the PWM and SPI tests
* Call these out in supported.yaml
Signed-off-by: Michael Hope <mlhx@google.com>
Remove the device_type = "memory" property from the PSRAM node. We make
the slightly arbitrary distinction of using 'mmio-sram' compatible for
memories that don't need some kinda of dram style configuration or may
be on die.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
For true mmio-sram, arc,iccm, arc,dccm nodes we should not be setting
device_type = "memory". This should be used for true DRAM regions of
memory and not on SoC SRAMs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
* Rename DT_SRAM_SIZE to DT_DRAM_SIZE since that is more correct
* Remove mmio-sram compatible since that is not correct for DRAM.
* Rename node label from sram0 to dram0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add support for wsen-itds 3-axis accel sensor, provides acceleration,
temperature data reading and supports configuring of output data rate,
operating mode and scale.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
The parameters for this fuel gauge depend on the hardware design and
the expected battery. These should not be defaulted to a value that
may be inappropriate. Require that they be explicitly provided.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Add Xplained-Pro header connector defined by Atmel. This allows
hardware with compatible headers to define the related GPIOs.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add Xplained header connector defined by Atmel. This allows hardware
with compatible headers to define the related GPIOs.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add support to STM IIS2DH the ultra-low-power highperformance
three-axis linear accelerometer.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add option to concatenate i2c transfers. If concatenation buffer size is
provided then transfers will be concatenated as long as there is space
left in buffer.
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
The generic SPI GPIO chip select support now respects devicetree flags
for signal active level. Update all cs-gpios properties to specify
active low.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
We deprecated a number of aspects of the DTS binding syntax in Zephyr
2.1. Remove the support for the deprecated syntax. Remove from docs
about the deprecated syntax as well.
Removed reference in release-notes-2.1.rst to legacy_binding_syntax
since that anchor doesn't exist anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
compatible = "arm,cortex-m33f" was already used for some time
(lpc55S6x, nrf9160...) without any related bindings.
Every works fine until you need to access one CPU node property
(eg. clock-frequency)...
Signed-off-by: Arnaud Mouiche <arnaud.mouiche@invoxia.com>
Several peripherals are non-functional in the ENG_A revision
of nRF5340 (Application MCU) so we delete the corresponding
DTS nodes in the device description.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Rename the nRF5340 QKAA variant .dtsi headers (Application
MCU) by adding an Engineering A (Eng A) suffix. This is done
to indicate that the headers should be explicitly used when
building for a board that contains the Engineeering A nrf5340
SoC variant.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We need to use CPUAPP and CPUNET instead of CPU0 and CPU1
terminology, because those terms are the ones used
throughout the DeviceTree definitions for nRF5340 SoC.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Move the definition of the number of MPU regions
(num-mpu-regions) in a SoC variant-specific header
instead of the common .dtsi for nRF5340 Application
MCU. This allows us to define different SoC variants
with different number of MPU regions available.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit renames the nrf5340_cpuapp_common.dtsi header
to nrf5340_cpuapp_peripherals.dtsi. This name is more
appropriate, as the header contains DT definitions for
peripherals, accessible from either Secure or Non-secure
execution environment (i.e. not accessible exclusively
by Secure or Non-Secure).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds the device tree TCC (Timer/Counter for Control
Applications) peripheral definitions for the Atmel SAM D5x and E5x
series SoCs.
The SAM D5x/E5x series SoCs have five instances of the TCC peripheral:
TCC# Channels Waveform Output Counter Size
0 6 8 24-bit
1 4 8 24-bit
2 3 3 16-bit
3 2 2 16-bit
4 2 2 16-bit
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Add support for STM32L0X using the generic STM32 backend. This is
quite a significant change since the L0 series uses a slightly
different flash controller. Refactor the generic backend to better
support different block sizes and the L0's register interface.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Add device tree bindings for the Semtech SX1261 and SX1262
radios. These will be used by Zephyr's LoRa drivers.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Adds optional device tree properties to set delays between spi chip
select assert/deassert and clock edges in the mcux dspi and lpspi
drivers. If these properties are not set, then the minimum supported
delays are used.
Verified that tests/drivers/spi/spi_loopback/ still passes on
mimxrt1050_evk (lpspi driver) and frdm_k64f (dspi driver).
Measured with a scope that the pcs-sck-delay and sck-pcs-delay times on
the first spi transaction in the test are reduced from 7.82 us to 20 ns
on mimxrt1050_evk.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add Nuvoton numicro series UART support, currently supports
only poll mode.
UART0 clock and pincontrol are directly configured, will be
replace when clock and gpio support is added.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Add initial support for nuvoton numicro m48x SoC series, basic
init and uart functionality are covered with gpio and clock
directly relies on HAL.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
The SAMD21 series has three timer/counters with a mix of channels and
resolutions. Note that the SAMD20 only has TC peripherals and no TCC
peripherals which is why the changes are in samd21.dtsi.
Signed-off-by: Michael Hope <mlhx@google.com>
The SAM0 Timer/Counter for Control Applications can act as a counter
or generator. Add a binding for the TCC in PWM mode and helper to
check the compat mode.
Signed-off-by: Michael Hope <mlhx@google.com>
Timer interrupts have been added for all STM32 SoC. H7 series already
had the interrupt definitions. The IRQ number and names have been taken
from the STM32Cube HAL header files.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The value of a label property isn't really the name of an API. It's
the name of a device, as passed to device_get_binding().
Let's just say that directly so people know what this means in
practice instead of what's currently used as the description, which is
harder to understand and not really accurate.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
RF SPDT switches used for RX/TX selection have often power enable pin
connected to MCU's GPIO, so it is possible to disable it to save power
when not doing any data transfers. Add 'antenna-enable-gpios' property
to support such designs.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Add support for TCXO power control using GPIO pin. Some boards
(including B-L072Z-LRWAN1 already supported in Zephyr) need delay
applied after powering on TCXO, so add device-tree property allowing to
configure that as well. Cache information about TCXO power status, so
subsequent requests to enable it will not result in unnecessary delays.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
There are several antenna path designs on SX1276 compatible boards in
the wild. B-L072Z-LRWAN1 board has dedicated enable pins for RFI, RFO
and PA_BOOST. This is exactly what this patch allows to
configure. Second variant of antenna selection is done with a single
GPIO pin, which controls RF SPDT switches (input or output). This is
also supported, when either 'rfo-enable-gpios' or
'pa-boost-enable-gpios' property is provided alone (RFO/PA_BOOST is
selected only when transmitting, so there is no need for explicit
'rfi-enable-gpios' configuration).
Drop requirement for 'power-amplifier-output' DT property when there is
either 'rfo-enable-gpios' or 'pa-boost-enable-gpios' configured. Fail
using BUILD_ASSERT() when neither is specified.
Make the SX1276SetAntSw() logic similar to loramac-node examples
implementation, so RFO/PA_BOOST is enabled only in
RFLR_OPMODE_TRANSMITTER.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
PA selection mainly depends on board design. So it looks like
device-tree is a better mechanism than Kconfig in this case. Use string
property with two possible values: "rfo" and "pa-boost".
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
With addition of flash_get_parameters API call, it is needed to provide
support for the API to flash drivers.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Add support for the polarity flag in the STM32 PWM driver.
STM32 boards using PWM have been updated accordingly.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Aliases defined for peripheral nodes in the nRF SoC definitions were
used in drivers to properly match the hardware instances.
After the drivers were converted to use the new DT API, these aliases
became needless.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Previously, DTS specification of physical RAM bounds did not
correspond to the actual bounds of system RAM as the first
megabyte was being skipped.
There were reasons for this - the first 1MB on PC-like systems
is a no-man's-land of reserved memory regions, but we need DTS
to accurately capture physical memory bounds.
Instead, we introduce a config option which can apply an offset
to the beginning of physical memory, and apply this to the "RAM"
region defined in the linker scripts.
This also fixes a problem where an extra megabyte was being
added to the size of system RAM.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Appropriate WS can be loaded automatically if
the display controller has integrated temperature
sensor or an external sensor is connected.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Enable GPIO as a workaround to enable some SPI slaves are not correctly
controlled using the Flexcomm SPI device.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Those MCUs have 2KB RAM and 16KB FLASH memory, but they are still
powerful enough to run small configuration of Zephyr RTOS.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
- Change default CPU Clock to 240MHz
(PLL is activated)
- I2C, UART will use sysclk from clock driver
- esp32_enable_peripheral replaced by
clock_control_on
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
- Support PLL for Higher Frequencies 80,160,240 MHz
- Support XTAL Frequencies 26MHz, 40MHz
- Clock Driver can't be disabled, because all of the other drivers
will depend on it to get their operating Frequency based on chosen
clock source (XTAL/PLL).
- Add needed references to BBPLL i2c bus ROM functions.
- Add `rtc` node to Device Tree.
- Since All Peripherals Frequency is depending on CPU_CLK Source,
`clock-source` property added to CPU node
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
Cleaned up flow control configuration. Added support for using only
cts or only rts.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The STM32L072 and STM32L073 comes with a hardware random number
generator. Add this to the device tree.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
This allows referencing the CPU in the board-specific DTS file.
Also fix warnings by making the addresses lower case.
Signed-off-by: Michael Hope <mlhx@google.com>
Adds a new LPTIM binding for stm32 soc,
based on the timer binding. This will makes a specific filter
on dt_compat_enabled("stm32,lptim")
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add test cases that verify various bits and pieces of the legacy
devicetree macros match the new APIs.
Writing these test cases without giving rise to deprecated macro
warnings which might break people's CI if they build with -Werror
requires turning off the __WARN() generation in
devicetree_legacy_unfixed.h. The entire file is deprecated at this
point and must be explicitly enabled with an opt-in Kconfig option, so
there isn't any harm in doing this.
Nevertheless, take a minimally invasive approach to avoiding __WARN()
generation in gen_legacy_defines.py, to avoid the possibility of
breakage. This code is basically frozen anyway, so hacks like this
won't cause maintainability problems since it isn't being actively
maintained.
Use the new tests as fodder for a migration guide from the old API in
the documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Remove some deprecated or obsolete functionality:
- the 'title:' key is now deprecated
- more than 2 levels of child-binding are now supported
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
At some point, "child-binding:" apparently only worked up to 2 levels
deep. That's not the case anymore, but add a regression test to make
sure that doesn't break. 3 levels deep ought to be enough for anyone.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The interrupts generated by the generic timer behave in
a level-sensitive manner. Change the DT to reflect the same.
Fixes: #25585
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add the missing node and bindings. This is a secure-mapped peripheral,
so do not add it to the common include file
nrf5340_cpuapp_common.dtsi.
Fixes: #25493
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
In aarch64 DTs, priority and flags cells have been swapped,
fix the same.
Correct interrupt property per the GIC binding document
looks like:
interrupts = <irq_type irq_num irq_flags irq_priority>;
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Adds the required #io-channel-cells property to kinetis k8x and kv5x
socs. We are now consistently defining this property for all
nxp,kinetis-adc16 compatible nodes.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Allow configuring the clock prescaler divider for the NXP Kinetis
FlexTimer. Setting the prescaler to a lower value allows for much
higher resolution/accuracy for the generated PWM waveforms.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The macro iterates through the list of child nodes in a DT_DRV_COMPAT
instance and invokes provided macro for each node.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Instead of having a Kconfig property, if there is no local-mac-address
property in the devicetree than we'll generate a unique MAC address
based on unique ID registers on the SoC.
We remove the local-mac-address properties in the SoC dtsi files to
match the default behavior that existed before (ie, unique MAC address)
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add definition of zephyr,random-mac-address property that conveys to a
driver to utilize a random MAC address if the driver supports this
feature.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add infineon XMC4 series UART support. Driver supports
only poll mode using XMCLib.
Out of 4 available UART's on SoC, only UART1 is confgired
by default in UART mode until GPIO & pinctrl support.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Add infineon xmc series with XMC4500 support. XMC series comes with,
- CPU operates upto 120MHz
- 3 RAM (PSRAM1 - code, DSRAM1 - data and DSRAM2 - communiation)
- upto 1MB flash
init: clock control & gpio is not done, so SoC initialization directly
relies on HAL. Core operating clock is stored in no_init section, which
is kept under DSRAM1. Only DSRAM1 is used until clock support. Using
PSRAM1 and DSRAM1 needs adaptation in linker script - planned for next
revision.
Note: SystemInit cannot be consumed directly due to vector table +
HAL linker dependency.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
For HPET devices, configure it with fixed delivery mode because HPET
timer interrupt is needed to fuel the scheduler for all CPUS.
For all other type of devices, like UART, I2C, GPIO, Ethernet, etc.
configure them as lowest priority delivery mode, in which IO APIC
delivers the interrupt to the processor core that is executing at the
lowest priority among all the processors listed in the specified
destination. In this case, the device drivers can avoid the trouble of
handling repeated interrupts delivered to all CPUS.
Signed-off-by: Zide Chen <zide.chen@intel.com>
The label property does not need to have its type set
explicitly to string, so remove it.
Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
By this commit USB audio class implementation is introduced
to Zephyr.
The Zephyr USB audio device class follows bellow
documentations:
- Universal Serial Bus specification rev2.0 (usb20.pdf)
- Universal Serial Bus Device Class Definition for Audio Devices
(audio10.pdf)
- Universal Serial Bus Device Class Definition for Audio Data Formats
(frmts10.pdf)
- Universal Serial Bus Device Class Definition for Terminal Types
(termt10.pdf)
Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
This commit adds support for nRF52820 development on nRF52833DK.
Changes afffects:
- Introduce files related to board description.
- Add blank documentation file (for future update).
- configuration files for build process.
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
This commit adds basic support for nRF52820 SoC.
Changes affect introducing:
- architecuture files (dtsi)
- configuration of nrfx drivers
- adaptation of inclusions based on chosen SoC
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
Add STM32F427. This is mainly aimed towards the stm32f427vi.
Changes:
- Add stm32f427 support based on previous work
done for the stm32f429.
- Rework currunt stm32f429 implimentation to now
be based on stm32f427.
- Introduce dedicated dtsi for the VI variant of both
stm32f427 and stm32f429. This is done to prevent stm32f4.dtsi
from being included twice.
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
Update dtsi and pinmux macros for stm32f7 family. Add sdmmc1 to dts file
for stm32f746g_disco. Also add board specific configuration file for
fat_fs sample.
Signed-off-by: Helge Juul <helge@fastmail.com>
Update the dtsi for stm32l471 (which the higher SoCs are based on) to
support the stm32-sdmmc disk access device. Enable the device for the
stm32l496g_disco board, and update the pinmuxing.
Note that the stm32l496g_disco board also has a card detect gpio
(MFX_GPIO8), but this is not supported yet. When not specified the
driver will assume a card is present.
Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
Add a disk access driver for the stm32 sdmmc component. The driver is
based around the stm32 cube HAL and uses the blocking API.
Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
Add initial support for Broadcom Viper SoC.
It has ARM Cortex-M7 and Cortex-A72 cores.
Signed-off-by: Arjun Jyothi <arjun.jyothi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add initial support for Decawave DW1000
IEEE 802.15.4-2011 UWB transceiver.
Driver has basic functionality. Additional functions such
as reading out timestamps and delayed TX were implemented
for test purposes, but also require support in the 802154
subsystem.
Register, sub-register, and defaults defines in the file
ieee802154_dw1000_regs.h are taken from the Decawave's
DW1000 driver for the Mynewt OS.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Binding used for LPC random number generator hardware.
Describes RNG device node in LPC5xxx SoCs device tree peripherals.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Add support for ADC on H7 series. Note that ADC1 and ADC2 share the same
register set, so it is added as "adc1_2".
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Convert i2s_sam_ssc driver to utilize devicetree. We replace Kconfig
options for specifying the DMA configuration (channel, DMA device name)
with getting that from devicetree. We also get pincfg from devicetree,
however we still have Kconfig sybmols to specify if the RF or RK pin is
enabled.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert sam_xdmac driver to utilize devicetree. As part of the
controller binding we specify that dmas should contain a channel and the
perid for the DMA transaction.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The DS3231 is an I2C real-time clock with internal temperature
compensated oscillator, maintaining civil time to 1 s precision with
nominal 2 ppm accuracy from 0-40 Cel.
The basic functionality is exposed as a counter that is always running
at 1 Hz. Much more functionality is exposed as driver-specific API,
including the ability to translate between the time scale of the DS3231
and the time scale of the Zephyr uptime clock. This allows correlation
of events in the system clock to UTC, TAI, or whatever time scale is
used to maintain the DS3231.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Add a driver that can handle several instances of AT45 family chips,
which are enabled by specifying DT nodes for them with the "compatible"
property set to "atmel,at45" and other required properties like JEDEC
ID, chip capacity, block and page size etc. configured accordingly.
The driver is only capable of using "power of 2" binary page sizes in
those chips and at initialization configures them to work in that mode
(unless it is already done).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This header is physically related to the Adafruit Feather, but uses a
different pin numbering and exposes a slightly different set of pins.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Once the TPM driver and the required configs have been added,
now this patch enables the usage of the PWM framework on KW41Z
SoCs. As such, the DTS gets the proper nodes and the pinmuxing
is done according to the configuration requested.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
The TPM (Timer/PWM Module) is a 2- to 8-channel timer which supports
input capture, output compare, and the generation of PWM signals to
control electric motor and power management applications.
This patch adds the driver and the binding necessary for instantiating
the driver. The work is based on the RV32M1 driver for TPM done by
Henrik Brix Andersen. A later patch will enable this driver to be used
for the KW41Z SoC, if PWM support is requested.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
* Define USB driver for base stm32wb device.
* Enable USB for the nucleo_wb55rg board.
* Properly initialize USB power + clock for the platform.
Signed-off-by: Pete Johanson <peter@peterjohanson.com>
This patch introduces the periph to/from memory dma transfer
using the dmamux feature and define new values
for dma cells on client side
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Reworked sam_gmac driver to get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from soc_pinmap.h that are no longer needed due to
getting all that information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Atmel SAM D5x and E5x series SoCs include the ARM memory protection
unit that supports up to 8 memory regions.
This commit adds the missing device tree MPU node to `samd5x.dtsi`,
which is used by both the SAM D5x and E5x series SoCs.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This patch is defining the DMA1 & 2 for the sm32l4 series
with 7 channels and support of mem2mem transfers
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This includes the dma cells as client for the spi
An example of the client part is defined in the dma.yaml
Consequently, bindings for the dmas property becomes then 'not required'
Including dma.yaml is not needed as dma properties
are now part of base.yaml
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add device tree nodes for the Digital-to-Analog (DAC) modules present
in the NXP Kinetis K6x series.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add device tree node for the Digital-to-Analog (DAC32) module present
in the NXP Kinetis KE1xF series.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add initial devicetree for the NXP LPC55S16. Only non-secure (ns)
access is supported for now.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Do not assume in the SoC level device trees that NXP Kinetis FlexTimer
nodes will always be configured as PWM. Instead, configure FlexTimer
nodes for PWM at the board level for NXP Kinetis boards.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rework the atom/linker.ld to match how ia32/linker.ld works with regards
to how PHYS_LOAD_ADDR & PHYS_RAM_ADDR are set based on CONFIG_XIP and
from which DT_PHYS_{RAM,LOAD}_ADDR defines. We update the minnowboard
dts and atom.dtsi files to keep in sync with this.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rework the devicetree to utilize new DT_INST macros and extract per
instance data for clocks from devicetree.
We add a property ('calib-offset') for the SAM{D,E}5x family of SoCs
that is the bit position offset from ADC0 BIASCOMP in the NVM Software
Calibration Area Mapping. For ADC0 this is typically 0 and for ADC1
this will be 14.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In STM32 can driver CAN2 instance need to know the base address
of CAN1 instance which is referenced as master can.
Add this information as an optional property to stm32 can binding.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
By defaut, only one uart is used as console.
Disable unused peripherals in dts to avoid
conflicts (issue #23475), save memory footprint,
and reduce the boot time.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Convert driver to use the new device tree macro's instead of
dts_fixup.h based macros. This moves us closer to removing both
dts_fixup.h and per instance Kconfig symbols.
The pinmux_mchp_xec is also being updated since it's using DT
from GPIO.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Convert driver to use the new device tree macro's instead of
dts_fixup.h based macros. This moves us closer to removing both
dts_fixup.h and per instance Kconfig symbols.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add local-mac-address on DT and enable it on rf2xx driver. If user
define local-mac-address this value will be used as default mac address.
Otherwise driver automatically add a random mac address.
On application level user can change default mac address using net_mgmt
command with NET_REQUEST_IEEE802154_SET_EXT_ADDR parameter defined on
include/net/ieee802154_mgmt.h header.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
